TMS320C6654: Inactive time of RESETFULL while POR is active

Again, RESETFUL must be low for at least 24 transitions of SYSCLK1 after POR has stabilized at a high level. This means that it MUST be low even when POR is active (low level).
This is clarified in both Datasheet & Hardware design Guide for Keystone Devices:

"5.1.2 RESETFULL
RESETFULL is an active-low signal that will reset all internal configuration registers to a known good state. RESETFULL performs all the same functions as POR and is also used to latch the BOOTMODE and configuration pin data. RESETFULL must be asserted (low) on a power-up while the clocks and power planes become stable, and RESETFULL must remain low until the specified time after POR has been released. For the timing requirements of POR and RESETFULL, see the device-specific data manual. Once POR has been released, the RESETFULL signal may be toggled at any time to place the KeyStone I device into a default state.
Both POR and RESET should be high before RESETFULL is deasserted, otherwise the device may not boot correctly.
The proper use of RESETFULL is required and must follow all timing requirements. See the device-specific data manual for additional RESETFULL details. RESETFULL and POR must be controlled separately. The KeyStone I part will not operate correctly
if they are tied together.
If POR is asserted due to an incorrect power supply voltage, then RESETFULL must also be asserted until the prescribed time after POR to assure that the proper configuration is latched into the device."

Why are you trying to deviate from TI recommendations?

Best Regards,
Yordan