RTOS/AM3359: EtherCAT Slave PHY issue

Hello David/Ross,

So we have two custom boards:

1. with TLK110 PHY chip and

2. with DP83848 PHY chip

The PSDK and PRU Industrial config is

Configuration 1:

• processor_sdk_rtos_am335x_3_03_00_04

• pdk_am335x_1_0_6

• PRU-ICSS-EtherCAT_Slave_01.00.03.01

• ethercat_slave_full_AM335x_arm project

• Code Composer Studio 7.1.0

Configuration 2:

• processor_sdk_rtos_am335x_4_00_00_04

• pdk_am335x_1_0_7

• PRU-ICSS-EtherCAT_Slave_01.00.04.02

• ethercat_slave_full_AM335x_arm project

• Code Composer Studio 7.1.0

We have tested the above configurations on custom board with TLK110 PHY chip and ethercat communication works fine.

The other board where the only difference is PHY chip i.e. DP83848, it is not working. The ethercat communication is not established with the TwinCAT(or any other ethercat master).

Based on the inputs from other e2e forums we tried the following on the 2nd custom board(DP83848):

1.  in tiescbsp.c, bsp_init(), before calling bsp_pruss_mdio_init(), we updated the following

mdioParamsInit.enhancedlink_enable = TIESC_MDIO_RX_LINK_DISABLE;

2. We compared the registers between TLK110 and DP83848. Based on the above analysis, we commented the code where TLK registers were getting written by the sample application code.

After this, the value of PHY registers are:

regards

Mohit

Hi Mohit

The MDIO MDIO ALIVE and LINK registers are valuable to use when assessing EtherCAT status

The MDIO is described in Section 14.3.8 MDIO of the AM335x TRM http://www.ti.com/lit/pdf/spruh73

The PRU-ICSS MDIO register set starts at @ 0x4a33_2400

The MDIO Alive register is updated by the MII Management I/F module if the PHY acknowledged the read

of the generic status register. In addition, any PHY register read transactions initiated by the host also

cause the MDIOAlive register to be updated.

ALIVE bits will be set for corresponding PHY addresses  

The MDIO PHY alive status register (MDIOALIVE) can be read in polling fashion until a PHY connected to the system responded, and the MDIO PHY link status register (MDIOLINK) can determine whether this PHY already has a link

Verify that the appropriate PHY addresses are being set in the MDIO user PHY select register (MDIOUSERPHYSELn),

Link polarity is of importance for EtherCAT if enhanced link detection is enabled, this can be disabled during MDIO init via DISABLE macro instead of ENABLE. This is defined in tiescbsp.h  and  tiescbsp.c.

The best way is to check this using MDIO link register and inserting ethernet cable from PC to DUT port and observing any change. If link register is zero with – no ports connected both links will be active HIGH. If port0 link connected and up, port0 is active LOW and you need to adjust this in link polarity field during mdio init.

 The MDIO is initialized by bsp_pruss_mdio_init . This API is documented in http://processors.wiki.ti.com/index.php/PRU_ICSS_EtherCAT_firmware_API_guide#bsp_pruss_mdio_init

David

Hello David,

The correct PHY addresses are getting set in MDIOUSERPHYSELn

We are using PHY addresses 1 and 3.

Here I am attaching the screenshot of MDIO registers when port 0 (having PHY address 1) is connected to Ethercat Master. We have disabled the enhanced link using the macro of tiescbsp.h

regards

Mohit

Mohit
It looks like you are paralleling what we would see on the ICE with Enhanced Link Detection disabled.
Let me quickly confirm with our team.
David