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TDA2xx : Starterware EDMA3 base addresses/number of PaRAM sets/L2SRAM global addresses clarification

Nik Trif
Prodigy 250 points

Hello, I'm using Vision SDK 2.10 and testing on a TDA2xx.

I'm trying to utilize EDMA using starterware_01_06_00_16 on a C66x core. That means that I want to use the C66x dedicated EDMA and not the system one. I have some questions regarding channel controller base addresses that are enlisted here: ...VISION_SDK_02_10_00_00\ti_components\drivers\starterware_01_06_00_16\include\c66x\tda2xx\soc.h.

These 3 are confusing.

#define SOC_DSP_EDMA_CC_BASE           (0x1d10000U)
#define SOC_DSP1_EDMA_CC_BASE         (0x40d10000U)
#define SOC_DSP2_EDMA_CC_BASE         (0x41510000U)

I know that the first one is local address when accessed from the DSP (and I have succesfully used that address before). Are the other two global addresses of corresponding EDMAs?

Also I found this:

#define SOC_EDMA_CC_BASE            (0x3300000U)

Is it the definition of the system EDMA base address? If so, how come it's not 0x43300000, when I used the system EDMA earlier with the EDMA3 LLD it was 0x43300000.

Also, another question that I have is about the number of PaRAM sets in the DSP dedicated EDMA.

Here I found that it is 128: https://e2e.ti.com/support/arm/automotive_processors/f/1021/p/553514/2029041#2029041

However, I would like to see a piece of documentation where I can find that information officially. I looked at this: http://www.ti.com/lit/an/sprac21/sprac21.pdf but couldn't find it anywhere. I also need to see the information about the 0x40000000 offset that needs to be added to L2SRAM allocated buffers' addresses in order to get their global address.

Thank you in advance.

  • 0
    TI__Mastermind 42515 points
    Hi Nik,

    I have forwarded your question to Starterware experts.

    Regards,
    Yordan
  • 0
    TI__Prodigy 660 points
    Hi Nik,

    1) Yes, SOC_DSP_EDMA_CC_BASE (0x1d10000U) is the local address of the DSP internal EDMA when accesses by the DSP itself.

    And yes, SOC_DSP1_EDMA_CC_BASE (0x40d10000U) and SOC_DSP2_EDMA_CC_BASE (0x41510000U) are the global (L3_MAIN) addresses of the corresponding DSP EDMAs.

    2) As per the DSP memory map (see 'Table 2-10. DSP Memory Map' in the TRM), it seems that the DSP has a direct/private access to the System EDMA at address 0x0330_0000. So SOC_EDMA_CC_BASE (0x3300000U) should be a definition of the System EDMA base address when accessed "privately" by the DSP.

    Otherwise, the global address of the System EDMA is indeed 0x43300000, as you noted.

    3) The number of PaRAM sets in DSP EDMA is documented in 'Table 16-82. EDMA Channel Controllers Configuration' in the TRM.

    I hope this helps.

    Regards,
    Vasil
  • 0 in reply to Vasil Kehayov
    Prodigy 250 points

    Hi Vasil,

    Thank you for your help, this cleared up all the confusion.

  • 0 in reply to Nik Trif
    Prodigy 250 points
    Hi, there's a few more questions I have about the DSP dedicated EDMA that I haven't been able to find in the TRM.

    1) How do the DSP core and EDMA access the internal and external memories in the sense of arbitrating the bus access between them? Does the EDMA have it's own bus which I found somewhere to be 128 bits wide or does it share it with the core?

    2) In the second link that I enclosed in the original post there is a recommendation about aligning source/destination addresses to the default burst size boundary. I'm not sure that I understand how aligning those improves performance since the data is being buffered in the transfer controller before it hopefully reaches the default burst size and then gets written. Is that related to the memory banks or something else?

    Thank you in advance.
  • 0 in reply to Nik Trif
    TI__Mastermind 42515 points
    Hi Nik,

    I have pinged an expert to comment on your new question.

    Regards,
    Yordan
  • 0 in reply to Yordan Kamenov
    TI__Mastermind 30245 points

    Hi Nik,

    The DSP CPU access goes through via the MDMA path and the EDMA accesses are through the EDMA path. Figure 5-1. DSP Subsystem Highlight in the TDA2x TRM will give you some idea. The arbitration to DSP Internal L1/L2 memories is done through the DSP L2 Interconnect and the external memory accesses are arbitrated through the L3 Interface. The buses for the DSP CPU and DMA access is not shared.

    Burst is a mechanism used by the interconnect to transfer a chunk of data to the destination using a single command, address. Data of the size of the burst is associated with that single command. When we transfer address/size that is not burst size aligned the starting/ending portion of the unalignment is sent out using an additional aligned address and byte enable bus is used to indicate how many bytes to write. These additional accesses if done many times would reduce the efficiency of the transfer.

    Hope this helps.

    Thanks and Regards,

    Piyali

  • 0 in reply to Piyali Goswami
    Prodigy 250 points
    Piyali,
    thank you for the answer.