Part Number: TMS320TCI6618
Hi, TI experts,
Could you help about this cache issue, what is the cache error indicate, and how could we fix it?
Background:
in TCI6618, We try to send event from same core 1 to core 1(core index start from 0). If we use use mfence after Emti_wb(), issue won't happen, if we use mfence without Emti_wb(), then cache issue would happen.
With same code, this issue only happen in TCI6618, but won't happen in K2K devices.
Issue:
oth L1P and L1D issue happen together.
L1P issue:
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- Line: 842 0x00006940 allocated from:0x1184e940 -> *:Emti_wbinv (o = 0x80)
- BIT ERROS DETECTED:
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lastExceptionType = 0xea07a = 958586
| bits 0 -19 : 958586 == EXCPHNDL_PRISYS_DMC_CMPA_EVT : CPU memory protection fault (L1D)
internalExceptionsCount = 0x0 = 0
externalExceptionsCount = 0x2 = 2
otherExceptionsCount = 0x0 = 0
exceptionReturnAddress = 0x118004dc = *:_odo_os_int_stub_stub (o = 0x00000120)
memProtFaultingAddress = 0x15000102 = 352321794
memProtFaultStatus = 0x120 = 288
| bit 5 : 1 == Supervisor read request
| bit 8 : 1 == Access was LOCAL access
memProtFaultStatusExtension = 0x0 = 0
mdmaErrorStatus = 0x20000d01 = 536874241
| bits 29-31 : 1 == MDMA read status error detected
| bits 0 -2 : 1 == Addressing error
| bits 8 -11 : XID: 0x000d
xmcMemProtFaultingAddress = 0x0 = 0
xmcMemProtFaultStatus = 0x0 = 0
busErrorStatus = 0x0 = 0
semErrorStatus = 0x0 = 0
tpccEmrReg = 0x0 = 0
tpccEmrhReg = 0x0 = 0
tpccQemrReg = 0x0 = 0
tpccCcerrReg = 0x0 = 0
tpccCcstatReg = 0x0 = 0
tptcErrstatReg = 0x0 = 0
tptcErrdetReg = 0x0 = 0
l1pErrorDetected = 0x0 = 0
l1pErrorInfo =
{
L1PEDADDR = 0x0 = 0
L1PEDSTAT = 0x0 = 0
}
Dave
