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Regarding evmDM6446 Hangs.

S.Yedire
Prodigy 10 points

Hi all,
I am currently working on  with viddec_copy examples my own codec algorithm. The codec algorithm is already ported on CCS v3.1 and 6416 DSK with no issue.
With my curren working code,I am able build a server with using below .cfg and .tcf file.  When did on h/w
CE_DEBUG=2 ./app.out ../<any.m2v out.yuv  | tee log1.log
The execution halts at "CV - VISA_call(visa=0x32b00, msg=0x4115bc80): messageId=0x000366d1, command=0x0"
I have double checked with my memory config in .cfg and .tcf and I did what ever in my limits
I also generated .map file to check the allocated sizes matche accordingly. I am still trying to work on this problem.
When I build without my codec algorithm in viddec_copy (another case but with same server.cfg and .tcf files) and this works fine on H/W.

I get this problem when I add call to my codec algorithm. I estimated my codec stack on CCS v 3.1 -1250.
I have given 65K for my codec stack but still hangs.

I have done allocations for my dynamic memory on Heap arround 213K and am sure Its allocated on Heap from log.

I have tried different sizes for stackSizes in .cfg file but it still did not work. It does not appear to be stack issue. 
Please check my .cfg,.tcf files below and let me know if I have made any problem.

Any help or suggestion would be appreciated on this problem. If you think this info is very less to suggest on this, I can send you the code or approach TI for support on this issue. Please let me know
Please find my log1.txt, .cfg(app and server), .tcf  below.
--------------------------------------------------------------------------------------------------------------------------------
Filename :log1.txt Obtained -CE_DEBUG=2 ./app.out ../<any.m2v> out.yuv | tee log1.txt
App-> Application started.
App-> Application started.
@0,476,901us: [+4 T:0x4003a6e8] OG - Global_init> This program was built with the following packages:
@0,477,311us: [+4 T:0x4003a6e8] OG -     package gnu.targets.rts470MV (/home/sandeep/dvsdk_1_30_01_41/xdc_3_00_02/packages/gnu/targets/rts470MV/) [1,0,0,0,1193542866293]
@0,477,408us: [+4 T:0x4003a6e8] OG -     package ti.xdais.dm (/home/sandeep/dvsdk_1_30_01_41/xdais_6_00_01/packages/ti/xdais/dm/) [1,0,4,0]
@0,477,483us: [+4 T:0x4003a6e8] OG -     package ti.xdais (/home/sandeep/dvsdk_1_30_01_41/xdais_6_00_01/packages/ti/xdais/) [1,2,1,0]
@0,477,552us: [+4 T:0x4003a6e8] OG -     package ti.sdo.utils.trace (/home/sandeep/dvsdk_1_30_01_41/framework_components_2_00_01/packages/ti/sdo/utils/trace/) [1,0,0,0]
@0,477,622us: [+4 T:0x4003a6e8] OG -     package ti.sdo.ce.utils.xdm (/home/sandeep/dvsdk_1_30_01_41/codec_engine_2_00_01/packages/ti/sdo/ce/utils/xdm/) [1,0,1,1200333457442]
@0,477,693us: [+4 T:0x4003a6e8] OG -     package dsplink.gpp (/home/sandeep/dvsdk_1_30_01_41/dsplink_140-05p1/packages/dsplink/gpp/) [1,1,0,0]
@0,477,759us: [+4 T:0x4003a6e8] OG -     package ti.sdo.linuxutils.cmem (/home/sandeep/dvsdk_1_30_01_41/cmem_2_00_01/packages/ti/sdo/linuxutils/cmem/) [2,0,0,0]
@0,477,826us: [+4 T:0x4003a6e8] OG -     package ti.sdo.fc.acpy3 (/home/sandeep/dvsdk_1_30_01_41/framework_components_2_00_01/packages/ti/sdo/fc/acpy3/) [1,0,2,0]
@0,477,893us: [+4 T:0x4003a6e8] OG -     package ti.sdo.fc.dman3 (/home/sandeep/dvsdk_1_30_01_41/framework_components_2_00_01/packages/ti/sdo/fc/dman3/) [1,0,3,0]
@0,477,961us: [+4 T:0x4003a6e8] OG -     package ti.sdo.ce.osal (/home/sandeep/dvsdk_1_30_01_41/codec_engine_2_00_01/packages/ti/sdo/ce/osal/) [2,0,1,1200333329943]
@0,478,028us: [+4 T:0x4003a6e8] OG -     package ti.sdo.ce.alg (/home/sandeep/dvsdk_1_30_01_41/codec_engine_2_00_01/packages/ti/sdo/ce/alg/) [1,0,0,1200332939285]
@0,478,099us: [+4 T:0x4003a6e8] OG -     package ti.catalog.c470 (/home/sandeep/dvsdk_1_30_01_41/xdc_3_00_02/packages/ti/catalog/c470/) [1,0,1,0,1192229332845]
@0,478,169us: [+4 T:0x4003a6e8] OG -     package ti.catalog.c6000 (/home/sandeep/dvsdk_1_30_01_41/xdc_3_00_02/packages/ti/catalog/c6000/) [1,0,0,0,1192229349164]
@0,478,236us: [+4 T:0x4003a6e8] OG -     package ti.platforms.evmDM6446 (/home/sandeep/dvsdk_1_30_01_41/bios_5_31_08/packages/ti/platforms/evmDM6446/) [1,0,0,0]
@0,478,304us: [+4 T:0x4003a6e8] OG -     package ti.sdo.ce (/home/sandeep/dvsdk_1_30_01_41/codec_engine_2_00_01/packages/ti/sdo/ce/) [1,0,5,1200332924185]
@0,478,372us: [+4 T:0x4003a6e8] OG -     package ti.sdo.ce.video (/home/sandeep/dvsdk_1_30_01_41/codec_engine_2_00_01/packages/ti/sdo/ce/video/) [1,0,2,1200333474655]
@0,478,438us: [+4 T:0x4003a6e8] OG -     package ti.sdo.ce.examples.codecs.viddec_copy (/home/sandeep/work/examples/ti/sdo/ce/examples/codecs/viddec_copy/) []
@0,478,505us: [+4 T:0x4003a6e8] OG -     package ti.sdo.ce.examples.codecs.videnc_copy (/home/sandeep/work/examples/ti/sdo/ce/examples/codecs/videnc_copy/) []
@0,478,569us: [+4 T:0x4003a6e8] OG -     package ti.sdo.ce.bioslog (/home/sandeep/dvsdk_1_30_01_41/codec_engine_2_00_01/packages/ti/sdo/ce/bioslog/) [1,0,1,1200332966901]
@0,478,636us: [+4 T:0x4003a6e8] OG -     package ti.sdo.ce.utils.trace (/home/sandeep/dvsdk_1_30_01_41/codec_engine_2_00_01/packages/ti/sdo/ce/utils/trace/) [1,0,1,1200333448031]
@0,478,704us: [+4 T:0x4003a6e8] OG -     package ceapp (/home/sandeep/work/examples/ti/sdo/ce/examples/apps/video_copy/dualcpu/evmDM6446/ceapp/) []
@0,480,391us: [+0 T:0x4003a6e8] OT - Thread_create> Enter (fxn=0x17d20, attrs=0x0)
@0,481,027us: [+0 T:0x4003a6e8] OT - Thread_create> Exit (task=0x32460)
@0,481,278us: [+2 T:0x4003a6e8] ti.sdo.ce.osal.alg - ALG_init> Enter
@0,482,266us: [+2 T:0x4003a6e8] ti.sdo.ce.osal.alg - ALG_init> Exit
@0,482,516us: [+6 T:0x4003a6e8] CE - Engine_init> CE debugging on (CE_DEBUG=2; allowed CE_DEBUG levels: 1=min, 2=good, 3=max)
@0,482,911us: [+0 T:0x4003a6e8] CE - Engine_open> Enter('video_copy', 0x0, 0xbefffc24)
@0,483,057us: [+0 T:0x4003a6e8] CE - rserverOpen('video_copy.x64P'), count = 0
@0,483,155us: [+0 T:0x4003a6e8] OP - Process_create> Enter(imageName='video_copy.x64P', linkCfg='(null)', attrs=0xbefffc28)
@0,599,725us: [+1 T:0x40948b60] OP - daemon> thread created.
@0,603,975us: [+0 T:0x40948b60] OP - Process_create_d> Enter(proc=0x32848)
@0,604,121us: [+2 T:0x40948b60] OP - Process_create_d> Initializing DSP PROC...
@0,604,227us: [+2 T:0x40948b60] OP - Process_create_d> Using DspLink config data for entry #0 [server 'video_copy.x64P']
@0,604,374us: [+2 T:0x40948b60] OP - Process_create_d> Adding DSP segment #0 to Link configuration: name='DDR2', startAddress=0x8fa00000, sizeInBytes=0x400000, shared=1
@0,604,499us: [+2 T:0x40948b60] OP - Process_create_d> Adding DSP segment #1 to Link configuration: name='DSPLINKMEM', startAddress=0x8fe00000, sizeInBytes=0x100000, shared=1
@0,604,603us: [+2 T:0x40948b60] OP - Process_create_d> Adding DSP segment #2 to Link configuration: name='RESET_VECTOR', startAddress=0x8ff00000, sizeInBytes=0x80, shared=0
@0,604,703us: [+2 T:0x40948b60] OP - Process_create_d> Adding DSP segment #3 to Link configuration: name='DDRALGHEAP', startAddress=0x88000000, sizeInBytes=0x7a00000, shared=0
@0,604,801us: [+2 T:0x40948b60] OP - Process_create_d> DOPOWERCONTROL was=0; now=0
@0,606,605us: [+2 T:0x40948b60] OP - Process_create_d> Attaching to DSP PROC...
@0,621,135us: [+2 T:0x40948b60] OP - Process_create_d> Opening MSGQ pool...
@0,621,777us: [+2 T:0x40948b60] OP - Process_create_d> Loading video_copy.x64P on DSP (1 args)...
@7,853,509us: [+2 T:0x40948b60] OP - Process_create_d> Starting DSP PROC...
@7,865,409us: [+2 T:0x40948b60] OP - Process_create_d> Opening remote transport...
@7,866,391us: [+2 T:0x40948b60] OP - Process_create_d> return (1)
@7,866,974us: [+0 T:0x4003a6e8] OP - Process_create> return (0x32848)
@7,867,115us: [+0 T:0x4003a6e8] CE - rserverOpen('video_copy.x64P'): 0x30cfc done.
@7,875,598us: [+0 T:0x4003a6e8] CE - checkServer(0x32818)
@7,876,371us: [+0 T:0x4003a6e8] CE - rmsInit> RMS initialized(0x32818); CE_DEBUG on, setting DSP trace mask to *+01234567,CR=67,ti.sdo.fc.dman3-2,ti.sdo.fc.dskt2-2,GT_prefix=1235,GT_time=3
@7,876,907us: [+0 T:0x4003a6e8] CE - Engine_setTrace> Enter(engine=0x32818, mask='*+01234567,CR=67,ti.sdo.fc.dman3-2,ti.sdo.fc.dskt2-2,GT_prefix=1235,GT_time=3')
@7,877,474us: [+1 T:0x4003a6e8] CE - Engine_setTrace> Requesting DSP set trace ...
@7,879,367us: [+0 T:0x4003a6e8] CE - Engine_setTrace> return(0)
[DSP] @0x000002de:[T:0x00000000] servers.video_copy.evmDM6446 - main> Welcome to DSP server's main().
[DSP] @0,029,345tk: [+0 T:0x8fa0348c] OG - Global_setSpecialTrace> enter(mask='*+01234567,CR=67,ti.sdo.fc.dman3-2,ti.sdo.fc.dskt2-2,GT_prefix=1235,GT_time=3')
[DSP] @0,029,473tk: [+4 T:0x8fa0348c] OG - Global_setSpecialTrace> This program was built with the following packages:
[DSP] @0,029,556tk: [+4 T:0x8fa0348c] OG -     package ti.targets.rts6000 (/home/sandeep/dvsdk_1_30_01_41/xdc_3_00_02/packages/ti/targets/rts6000/) [1,0,0,0,1193543029447]
[DSP] @0,029,668tk: [+4 T:0x8fa0348c] OG -     package ti.sdo.fc.dman3 (/home/sandeep/dvsdk_1_30_01_41/framework_components_2_00_01/packages/ti/sdo/fc/dman3/) [1,0,3,0]
[DSP] @0,029,777tk: [+4 T:0x8fa0348c] OG -     package ti.psl (/home/sandeep/dvsdk_1_30_01_41/bios_5_31_08/packages/ti/psl/) [5,0,0,0]
[DSP] @0,029,866tk: [+4 T:0x8fa0348c] OG -     package ti.rtdx (/home/sandeep/dvsdk_1_30_01_41/bios_5_31_08/packages/ti/rtdx/) []
[DSP] @0,029,953tk: [+4 T:0x8fa0348c] OG -     package ti.bios (/home/sandeep/dvsdk_1_30_01_41/bios_5_31_08/packages/ti/bios/) [5,2,3,20,0]
[DSP] @0,030,045tk: [+4 T:0x8fa0348c] OG -     package ti.sdo.utils.trace (/home/sandeep/dvsdk_1_30_01_41/framework_components_2_00_01/packages/ti/sdo/utils/trace/) [1,0,0,0]
[DSP] @0,030,158tk: [+4 T:0x8fa0348c] OG -     package ti.sdo.fc.dskt2 (/home/sandeep/dvsdk_1_30_01_41/framework_components_2_00_01/packages/ti/sdo/fc/dskt2/) [1,0,3,0]
[DSP] @0,030,268tk: [+4 T:0x8fa0348c] OG -     package ti.xdais.dm (/home/sandeep/dvsdk_1_30_01_41/xdais_6_00_01/packages/ti/xdais/dm/) [1,0,4,0]
[DSP] @0,030,364tk: [+4 T:0x8fa0348c] OG -     package ti.xdais (/home/sandeep/dvsdk_1_30_01_41/xdais_6_00_01/packages/ti/xdais/) [1,2,1,0]
[DSP] @0,030,456tk: [+4 T:0x8fa0348c] OG -     package ti.sdo.ce.node (/home/sandeep/dvsdk_1_30_01_41/codec_engine_2_00_01/packages/ti/sdo/ce/node/) [1,0,0,1200333318794]
[DSP] @0,030,567tk: [+4 T:0x8fa0348c] OG -     package ti.sdo.ce.utils.xdm (/home/sandeep/dvsdk_1_30_01_41/codec_engine_2_00_01/packages/ti/sdo/ce/utils/xdm/) [1,0,1,1200333457442]
[DSP] @0,030,684tk: [+4 T:0x8fa0348c] OG -     package ti.bios.utils (/home/sandeep/dvsdk_1_30_01_41/biosutils_1_00_02/packages/ti/bios/utils/) [2,0,0,22,0]
[DSP] @0,030,786tk: [+4 T:0x8fa0348c] OG -     package dsplink.dsp (/home/sandeep/dvsdk_1_30_01_41/dsplink_140-05p1/packages/dsplink/dsp/) [1,1,0,0]
[DSP] @0,030,884tk: [+4 T:0x8fa0348c] OG -     package ti.sdo.fc.acpy3 (/home/sandeep/dvsdk_1_30_01_41/framework_components_2_00_01/packages/ti/sdo/fc/acpy3/) [1,0,2,0]
[DSP] @0,030,993tk: [+4 T:0x8fa0348c] OG -     package ti.sdo.ce.osal (/home/sandeep/dvsdk_1_30_01_41/codec_engine_2_00_01/packages/ti/sdo/ce/osal/) [2,0,1,1200333329943]
[DSP] @0,031,110tk: [+4 T:0x8fa0348c] OG -     package ti.sdo.ce.alg (/home/sandeep/dvsdk_1_30_01_41/codec_engine_2_00_01/packages/ti/sdo/ce/alg/) [1,0,0,1200332939285]
[DSP] @0,031,219tk: [+4 T:0x8fa0348c] OG -     package ti.catalog.c6000 (/home/sandeep/dvsdk_1_30_01_41/xdc_3_00_02/packages/ti/catalog/c6000/) [1,0,0,0,1192229349164]
[DSP] @0,031,328tk: [+4 T:0x8fa0348c] OG -     package ti.platforms.evmDM6446 (/home/sandeep/dvsdk_1_30_01_41/bios_5_31_08/packages/ti/platforms/evmDM6446/) [1,0,0,0]
[DSP] @0,031,437tk: [+4 T:0x8fa0348c] OG -     package ti.sdo.ce (/home/sandeep/dvsdk_1_30_01_41/codec_engine_2_00_01/packages/ti/sdo/ce/) [1,0,5,1200332924185]
[DSP] @0,031,542tk: [+4 T:0x8fa0348c] OG -     package ti.sdo.ce.bioslog (/home/sandeep/dvsdk_1_30_01_41/codec_engine_2_00_01/packages/ti/sdo/ce/bioslog/) [1,0,1,1200332966901]
[DSP] @0,031,656tk: [+4 T:0x8fa0348c] OG -     package ti.sdo.ce.video (/home/sandeep/dvsdk_1_30_01_41/codec_engine_2_00_01/packages/ti/sdo/ce/video/) [1,0,2,1200333474655]
[DSP] @0,031,768tk: [+4 T:0x8fa0348c] OG -     package ti.sdo.ce.examples.codecs.viddec_copy (/home/sandeep/work/examples/ti/sdo/ce/examples/codecs/viddec_copy/) []
[DSP] @0,031,875tk: [+4 T:0x8fa0348c] OG -     package ti.sdo.ce.examples.codecs.videnc_copy (/home/sandeep/work/examples/ti/sdo/ce/examples/codecs/videnc_copy/) []
[DSP] @0,031,983tk: [+4 T:0x8fa0348c] OG -     package ti.sdo.ce.examples.servers.video_copy.evmDM6446 (/home/sandeep/work/examples/ti/sdo/ce/examples/servers/video_copy/evmDM6446/) []
[DSP] @0,032,103tk: [+0 T:0x8fa0348c] OG - Global_setSpecialTrace> return
@7,895,278us: [+0 T:0x4003a6e8] CE - Engine_open> return(206872)
TraceUtil_start> note: CE_DEBUG env. var is set, so TraceUtil is not active (unset CE_DEBUG if you need TraceUtil)
@7,895,520us: [+0 T:0x4003a6e8] ti.sdo.ce.video.VIDENC - VIDENC_create> Enter (engine=0x32818, name='videnc_copy', params=0x0)
@7,895,656us: [+0 T:0x4003a6e8] CV - VISA_create(0x32818, 'videnc_copy', 0x0, 0x828, 'ti.sdo.ce.video.IVIDENC')
@7,895,755us: [+0 T:0x4003a6e8] CV - VISA_create2(0x32818, 'videnc_copy', 0x0, 0x0, 0x828, 'ti.sdo.ce.video.IVIDENC')
@7,895,914us: [+0 T:0x4003a6e8] CE - Engine_createNode(0x32818, 'videnc_copy', 828, 0x0, 0x0, 0xbefffc28)
@7,898,354us: [+4 T:0x4003a6e8] CE - Engine_createNode> created node(stdIn=0x2, stdOut=0x10001, msgq=0x32ac0, algName='videnc_copy', rmsNode=0x8fa0c758, algHandle=0x8fa0c838)
[DSP] @0,072,050tk: [+0 T:0x8fa0348c] OM - Memory_alloc> Enter(size=0x18)
[DSP] @0,072,108tk: [+0 T:0x8fa0348c] OM - Memory_alloc> return (0x8fa0c758)
[DSP] @0,072,170tk: [+0 T:0x8fa0348c] OM - Memory_alloc> Enter(size=0xe)
[DSP] @0,072,225tk: [+0 T:0x8fa0348c] OM - Memory_alloc> return (0x8fa0c770)
[DSP] @0,072,289tk: [+0 T:0x8fa0348c] OM - Memory_alloc> Enter(size=0x20)
[DSP] @0,072,344tk: [+0 T:0x8fa0348c] OM - Memory_alloc> return (0x8fa0c780)
[DSP] @0,072,402tk: [+0 T:0x8fa0348c] OM - Memory_alloc> Enter(size=0x24)
[DSP] @0,072,457tk: [+0 T:0x8fa0348c] OM - Memory_alloc> return (0x8fa0c7a0)
[DSP] @0,072,543tk: [+0 T:0x8fa0348c] ti.sdo.ce.video.VIDENC - VIDENC_create> Enter (engine=0x0, name='videnc_copy', params=0x0)
[DSP] @0,072,647tk: [+0 T:0x8fa0348c] CV - VISA_create(0x0, 'videnc_copy', 0x0, 0x828, 'ti.sdo.ce.video.IVIDENC')
[DSP] @0,072,733tk: [+0 T:0x8fa0348c] CV - VISA_create2(0x0, 'videnc_copy', 0x0, 0x0, 0x828, 'ti.sdo.ce.video.IVIDENC')
[DSP] @0,072,834tk: [+0 T:0x8fa0348c] CE - Engine_open> Enter('local', 0x8fa0b1a8, 0x0)
[DSP] @0,072,902tk: [+0 T:0x8fa0348c] OM - Memory_alloc> Enter(size=0x2c)
[DSP] @0,072,957tk: [+0 T:0x8fa0348c] OM - Memory_alloc> return (0x8fa0c808)
[DSP] @0,073,023tk: [+0 T:0x8fa0348c] CE - Engine_open> return(-1885288440)
[DSP] @0,073,095tk: [+0 T:0x8fa0348c] OM - Memory_alloc> Enter(size=0x24)
[DSP] @0,073,150tk: [+0 T:0x8fa0348c] OM - Memory_alloc> return (0x8fa0c838)
[DSP] @0,073,213tk: [+0 T:0x8fa0348c] ti.sdo.ce.alg.Algorithm - Algorithm_create> Enter(fxns=0x8fa7f314, idma3Fxns=0x0, params=0x0, attrs=0x8fa0b2d4)
[DSP] @0,073,322tk: [+0 T:0x8fa0348c] OM - Memory_alloc> Enter(size=0x10)
[DSP] @0,073,377tk: [+0 T:0x8fa0348c] OM - Memory_alloc> return (0x8fa0c860)
[DSP] @0,073,447tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_init> Enter
[DSP] @0,073,531tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_init> Exit
[DSP] @0,073,585tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - DSKT2_createAlg> Enter (scratchId=0, fxns=0x8fa7f314, parentAlg=0x0, params=0x0)
[DSP] @0,073,686tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_init> Enter
[DSP] @0,073,739tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_init> Exit
[DSP] @0,073,795tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - DSKT2_createAlg3> Enter (scratchId=0, fxns=0x8fa7f314, parentAlg=0x0, params=0x0, extHeapId=0, singleHeap=0)
[DSP] @0,073,943tk: [+0 T:0x8fa0348c] ti.sdo.ce.examples.codecs.videnc_copy - VIDENCCOPY_TI_alloc(0x0, 0x8fa0b140, 0x880005c0)
[DSP] @0,074,037tk: [+2 T:0x8fa0348c] ti.sdo.fc.dskt2 - DSKT2_createAlg3> Num memory recs requested 1
[DSP] @0,074,115tk: [+4 T:0x8fa0348c] ti.sdo.fc.dskt2 - DSKT2_createAlg3> Requested memTab[0]: size=0x4, align=0x0, space=IALG_EXTERNAL, attrs=IALG_PERSIST
[DSP] @0,074,227tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_assignInstanceMemory> Enter (scratchId=0, numRecs=1, extHeapId=1)
[DSP] @0,074,321tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_usesInternalScratch> Enter (numRecs=1)
[DSP] @0,074,394tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_usesInternalScratch> Exit (returnVal=0)
[DSP] @0,074,472tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_allocateInDesignatedSpace> Enter (index=0, ialgSpace=IALG_EXTERNAL, extHeapId=1)
[DSP] @0,074,573tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_allocateInDesignatedSpace> Exit (returnVal=1)
[DSP] @0,074,653tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_usesInternalScratch> Enter (numRecs=1)
[DSP] @0,074,725tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_usesInternalScratch> Exit (returnVal=0)
[DSP] @0,074,797tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_assignInstanceMemory> Exit (returnVal=1)
[DSP] @0,074,871tk: [+4 T:0x8fa0348c] ti.sdo.fc.dskt2 - DSKT2_createAlg3> Allocated memTab[0]: base=0x88000610, size=0x4, align=0x0, space=IALG_EXTERNAL, attrs=IALG_PERSIST
[DSP] @0,074,999tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_enqueueMemTab> Enter (segId=1, memTabSize=80, numRecs=1, extHeapId=1)
[DSP] @0,075,112tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_enqueueMemTab> Exit (status=TRUE)
[DSP] @0,075,186tk: [+0 T:0x8fa0348c] ti.sdo.ce.examples.codecs.videnc_copy - VIDENCCOPY_TI_initObj(0x88000610, 0x880005c0, 0x0, 0x0)
[DSP] @0,075,285tk: [+4 T:0x8fa0348c] ti.sdo.fc.dskt2 - DSKT2_createAlg3> Algorithm init successful.
[DSP] @0,075,357tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - DSKT2_createAlg3> Exit (algHandle=0x88000610)
[DSP] @0,075,432tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - DSKT2_createAlg> Exit (algHandle=0x88000610)
[DSP] @0,075,508tk: [+0 T:0x8fa0348c] ti.sdo.ce.alg.Algorithm - Algorithm_create> return (0x8fa0c860)
[DSP] @0,075,587tk: [+0 T:0x8fa0348c] ti.sdo.ce.video.VIDENC - VIDENC_create> return (0x8fa0c838)
[DSP] @0,075,663tk: [+4 T:0x8fa0348c] OT - Thread_create > name: "videnc_copy#0", pri:  -1, stack size:  4096, stack seg: 0
@8,240,671us: [+2 T:0x4003a6e8] CE - Engine_createNode> Returning 0x32a98
@8,240,861us: [+5 T:0x4003a6e8] CV - VISA_create> remote codec created (name='videnc_copy', localQueueID=0x10001, remoteQueueID=0x0002)
@8,240,979us: [+0 T:0x4003a6e8] ti.sdo.ce.video.VIDENC - VIDENC_create> return (0x32a70)
@8,241,098us: [+0 T:0x4003a6e8] ti.sdo.ce.video.VIDDEC - VIDDEC_create> Enter (engine=0x32818, name='viddec_copy', params=0x0)
@8,241,196us: [+0 T:0x4003a6e8] CV - VISA_create(0x32818, 'viddec_copy', 0x0, 0x836, 'ti.sdo.ce.video.IVIDDEC')
@8,241,283us: [+0 T:0x4003a6e8] CV - VISA_create2(0x32818, 'viddec_copy', 0x0, 0x0, 0x836, 'ti.sdo.ce.video.IVIDDEC')
@8,241,423us: [+0 T:0x4003a6e8] CE - Engine_createNode(0x32818, 'viddec_copy', 836, 0x0, 0x0, 0xbefffc28)
@8,245,383us: [+4 T:0x4003a6e8] CE - Engine_createNode> created node(stdIn=0x3, stdOut=0x10002, msgq=0x32b50, algName='viddec_copy', rmsNode=0x8fa0d908, algHandle=0x8fa0d9a0)
[DSP] @0,873,755tk: [+0 T:0x8fa0348c] OM - Memory_alloc> Enter(size=0x18)
[DSP] @0,873,820tk: [+0 T:0x8fa0348c] OM - Memory_alloc> return (0x8fa0d908)
[DSP] @0,873,881tk: [+0 T:0x8fa0348c] OM - Memory_alloc> Enter(size=0xe)
[DSP] @0,873,935tk: [+0 T:0x8fa0348c] OM - Memory_alloc> return (0x8fa0d920)
[DSP] @0,873,999tk: [+0 T:0x8fa0348c] OM - Memory_alloc> Enter(size=0x20)
[DSP] @0,874,054tk: [+0 T:0x8fa0348c] OM - Memory_alloc> return (0x8fa0d930)
[DSP] @0,874,113tk: [+0 T:0x8fa0348c] OM - Memory_alloc> Enter(size=0x24)
[DSP] @0,874,168tk: [+0 T:0x8fa0348c] OM - Memory_alloc> return (0x8fa0d950)
[DSP] @0,874,252tk: [+0 T:0x8fa0348c] ti.sdo.ce.video.VIDDEC - VIDDEC_create> Enter (engine=0x0, name='viddec_copy', params=0x0)
[DSP] @0,874,344tk: [+0 T:0x8fa0348c] CV - VISA_create(0x0, 'viddec_copy', 0x0, 0x836, 'ti.sdo.ce.video.IVIDDEC')
[DSP] @0,874,427tk: [+0 T:0x8fa0348c] CV - VISA_create2(0x0, 'viddec_copy', 0x0, 0x0, 0x836, 'ti.sdo.ce.video.IVIDDEC')
[DSP] @0,874,534tk: [+0 T:0x8fa0348c] OM - Memory_alloc> Enter(size=0x24)
[DSP] @0,874,589tk: [+0 T:0x8fa0348c] OM - Memory_alloc> return (0x8fa0d9a0)
[DSP] @0,874,649tk: [+0 T:0x8fa0348c] ti.sdo.ce.alg.Algorithm - Algorithm_create> Enter(fxns=0x8fa7f2bc, idma3Fxns=0x0, params=0x0, attrs=0x8fa0b2d4)
[DSP] @0,874,758tk: [+0 T:0x8fa0348c] OM - Memory_alloc> Enter(size=0x10)
[DSP] @0,874,813tk: [+0 T:0x8fa0348c] OM - Memory_alloc> return (0x8fa0d9c8)
[DSP] @0,874,874tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_init> Enter
[DSP] @0,874,928tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_init> Exit
[DSP] @0,874,981tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - DSKT2_createAlg> Enter (scratchId=0, fxns=0x8fa7f2bc, parentAlg=0x0, params=0x0)
[DSP] @0,875,080tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_init> Enter
[DSP] @0,875,134tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_init> Exit
[DSP] @0,875,186tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - DSKT2_createAlg3> Enter (scratchId=0, fxns=0x8fa7f2bc, parentAlg=0x0, params=0x0, extHeapId=0, singleHeap=0)
[DSP] @0,875,333tk: [+0 T:0x8fa0348c] ti.sdo.ce.examples.codecs.viddec_copy - VIDDECCOPY_TI_alloc(0x0, 0x88000630, 0x8fa0d9c8)
[DSP] @0,875,426tk: [+0 T:0x8fa0348c] ti.sdo.ce.examples.codecs.viddec_copy - VIDDECCOPY_TI_alloc()-sizeof(VIDDECCOPY_TI_Obj)= 213384
[DSP] @0,875,519tk: [+2 T:0x8fa0348c] ti.sdo.fc.dskt2 - DSKT2_createAlg3> Num memory recs requested 1
[DSP] @0,875,594tk: [+4 T:0x8fa0348c] ti.sdo.fc.dskt2 - DSKT2_createAlg3> Requested memTab[0]: size=0x34188, align=0x0, space=IALG_EXTERNAL, attrs=IALG_PERSIST
[DSP] @0,875,717tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_assignInstanceMemory> Enter (scratchId=0, numRecs=1, extHeapId=1)
[DSP] @0,875,807tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_usesInternalScratch> Enter (numRecs=1)
[DSP] @0,875,879tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_usesInternalScratch> Exit (returnVal=0)
[DSP] @0,875,955tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_allocateInDesignatedSpace> Enter (index=0, ialgSpace=IALG_EXTERNAL, extHeapId=1)
[DSP] @0,878,405tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_allocateInDesignatedSpace> Exit (returnVal=1)
[DSP] @0,878,511tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_usesInternalScratch> Enter (numRecs=1)
[DSP] @0,878,583tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_usesInternalScratch> Exit (returnVal=0)
[DSP] @0,878,656tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_assignInstanceMemory> Exit (returnVal=1)
[DSP] @0,878,730tk: [+4 T:0x8fa0348c] ti.sdo.fc.dskt2 - DSKT2_createAlg3> Allocated memTab[0]: base=0x88000680, size=0x34188, align=0x0, space=IALG_EXTERNAL, attrs=IALG_PERSIST
[DSP] @0,878,864tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_enqueueMemTab> Enter (segId=1, memTabSize=80, numRecs=1, extHeapId=1)
[DSP] @0,878,969tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - _DSKT2_enqueueMemTab> Exit (status=TRUE)
[DSP] @0,879,614tk: [+2 T:0x8fa0348c] ti.sdo.ce.examples.codecs.viddec_copy - VIDDECCOPY_TI_initObj> Processed  dec->DecoderControlVar.Quiet_Flag= 0 bytes.
[DSP] @0,879,723tk: [+0 T:0x8fa0348c] ti.sdo.ce.examples.codecs.viddec_copy - VIDDECCOPY_TI_initObj(0x88000680, 0x0, 0x8fa0b2d4, 0x1)
[DSP] @0,879,820tk: [+4 T:0x8fa0348c] ti.sdo.fc.dskt2 - DSKT2_createAlg3> Algorithm init successful.
[DSP] @0,879,891tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - DSKT2_createAlg3> Exit (algHandle=0x88000680)
[DSP] @0,879,969tk: [+0 T:0x8fa0348c] ti.sdo.fc.dskt2 - DSKT2_createAlg> Exit (algHandle=0x88000680)
[DSP] @0,880,046tk: [+0 T:0x8fa0348c] ti.sdo.ce.alg.Algorithm - Algorithm_create> return (0x8fa0d9c8)
[DSP] @0,880,125tk: [+0 T:0x8fa0348c] ti.sdo.ce.video.VIDDEC - VIDDEC_create> return (0x8fa0d9a0)
[DSP] @0,880,201tk: [+4 T:0x8fa0348c] OT - Thread_create > name: "viddec_copy#1", pri:  -1, stack size:  65536, stack seg: 0
@8,586,919us: [+2 T:0x4003a6e8] CE - Engine_createNode> Returning 0x32b28
@8,587,133us: [+5 T:0x4003a6e8] CV - VISA_create> remote codec created (name='viddec_copy', localQueueID=0x10002, remoteQueueID=0x0003)
@8,587,252us: [+0 T:0x4003a6e8] ti.sdo.ce.video.VIDDEC - VIDDEC_create> return (0x32b00)
CEapp-> Allocating contiguous buffer for 'input data' of size 2048...
@8,587,585us: [+4 T:0x4003a6e8] OM - Memory_contigAlloc> CMEM_alloc(2048) = 0x411c9000.
@8,587,713us: [+4 T:0x4003a6e8] OM - Memory_contigAlloc> CMEM_getPhys(0x411c9000) = 0x87ffd000.
CEapp-> Allocating contiguous buffer for 'encoded data' of size 2048...
@8,587,949us: [+4 T:0x4003a6e8] OM - Memory_contigAlloc> CMEM_alloc(2048) = 0x411ca000.
@8,588,071us: [+4 T:0x4003a6e8] OM - Memory_contigAlloc> CMEM_getPhys(0x411ca000) = 0x87ffe000.
CEapp-> Allocating contiguous buffer for 'output data' of size 2048...
@8,588,300us: [+4 T:0x4003a6e8] OM - Memory_contigAlloc> CMEM_alloc(2048) = 0x411cb000.
@8,588,448us: [+4 T:0x4003a6e8] OM - Memory_contigAlloc> CMEM_getPhys(0x411cb000) = 0x87fff000.
@8,588,565us: [+0 T:0x4003a6e8] ti.sdo.ce.video.VIDENC - VIDENC_control> Enter (handle=0x32a70, id=0, params=0xbefffc40, status=0xbefffbb0
@8,588,675us: [+5 T:0x4003a6e8] CV - VISA_allocMsg> Allocating message for messageId=0x0002fed7
@8,588,766us: [+0 T:0x4003a6e8] CV - VISA_call(visa=0x32a70, msg=0x4115ac80): messageId=0x0002fed7, command=0x1
[DSP] @1,678,889tk: [+5 T:0x8fa0c8b4] CN - NODE> 0x8fa0c780(videnc_copy#0) call(algHandle=0x8fa0c838, msg=0x8fe06c80); messageId=0x0002fed7
[DSP] @1,679,031tk: [+0 T:0x8fa0c8b4] ti.sdo.ce.video.VIDENC - VIDENC_control> Enter (handle=0x8fa0c838, id=0, params=0x8fe06cb4, status=0x8fe06cdc
[DSP] @1,679,154tk: [+5 T:0x8fa0c8b4] CV - VISA_enter(visa=0x8fa0c838): algHandle = 0x8fa0c860
[DSP] @1,679,234tk: [+0 T:0x8fa0c8b4] ti.sdo.ce.alg.Algorithm - Algorithm_activate> Enter(handle=0x8fa0c860)
[DSP] @1,679,315tk: [+0 T:0x8fa0c8b4] ti.sdo.fc.dskt2 - DSKT2_activateAlg> Enter (scratchId=0, alg=0x88000610)
[DSP] @1,679,406tk: [+4 T:0x8fa0c8b4] ti.sdo.fc.dskt2 - DSKT2_activateAlg> Real activation of algorithm 0x88000610
[DSP] @1,679,493tk: [+0 T:0x8fa0c8b4] ti.sdo.ce.examples.codecs.videnc_copy - VIDENCCOPY_TI_activate(0x88000610)
[DSP] @1,679,575tk: [+0 T:0x8fa0c8b4] ti.sdo.fc.dskt2 - DSKT2_activateAlg> Exit
[DSP] @1,679,634tk: [+0 T:0x8fa0c8b4] ti.sdo.ce.alg.Algorithm - Algorithm_activate> return
[DSP] @1,679,702tk: [+0 T:0x8fa0c8b4] ti.sdo.ce.examples.codecs.videnc_copy - VIDENCCOPY_TI_control(0x88000610, 0x0, 0x8fe06cb4, 0x8fe06cdc)
[DSP] @1,679,807tk: [+5 T:0x8fa0c8b4] CV - VISA_exit(visa=0x8fa0c838): algHandle = 0x8fa0c860
[DSP] @1,679,883tk: [+0 T:0x8fa0c8b4] ti.sdo.ce.alg.Algorithm - Algorithm_deactivate> Enter(handle=0x8fa0c860)
[DSP] @1,679,965tk: [+0 T:0x8fa0c8b4] ti.sdo.fc.dskt2 - DSKT2_deactivateAlg> Enter (scratchId=0, algHandle=0x88000610)
[DSP] @1,680,055tk: [+4 T:0x8fa0c8b4] ti.sdo.fc.dskt2 - DSKT2_deactivateAlg> Lazy deactivate of algorithm 0x88000610
[DSP] @1,680,142tk: [+0 T:0x8fa0c8b4] ti.sdo.fc.dskt2 - DSKT2_deactivateAlg> Exit
[DSP] @1,680,203tk: [+0 T:0x8fa0c8b4] ti.sdo.ce.alg.Algorithm - Algorithm_deactivate> return
[DSP] @1,680,271tk: [+0 T:0x8fa0c8b4] ti.sdo.ce.video.VIDENC - VIDENC_control> Exit (handle=0x8fa0c838, retVal=0x0)
[DSP] @1,680,356tk: [+5 T:0x8fa0c8b4] CN - NODE> returned from call(algHandle=0x8fa0c838, msg=0x8fe06c80); messageId=0x0002fed7
@8,592,528us: [+0 T:0x4003a6e8] CV - VISA_call Completed: messageId=0x0002fed7, command=0x1, return(status=0)
@8,592,654us: [+5 T:0x4003a6e8] CV - VISA_freeMsg(0x32a70, 0x4115ac80): Freeing message with messageId=0x0002fed7
@9,270,216us: [+0 T:0x4003a6e8] ti.sdo.ce.video.VIDENC - VIDENC_control> Exit (handle=0x32a70, retVal=0x0)
@9,270,347us: [+0 T:0x4003a6e8] ti.sdo.ce.video.VIDDEC - VIDDEC_control> Enter (handle=0x32b00, id=0, params=0xbefffc68, status=0xbefffb08
@9,270,452us: [+5 T:0x4003a6e8] CV - VISA_allocMsg> Allocating message for messageId=0x0003e6d2
@9,270,537us: [+0 T:0x4003a6e8] CV - VISA_call(visa=0x32b00, msg=0x4115bc80): messageId=0x0003e6d2, command=0x1
[DSP] @3,260,798tk: [+5 T:0x8fa0da1c] CN - NODE> 0x8fa0d930(viddec_copy#1) call(algHandle=0x8fa0d9a0, msg=0x8fe07c80); messageId=0x0003e6d2
[DSP] @3,260,917tk: [+0 T:0x8fa0da1c] ti.sdo.ce.video.VIDDEC - VIDDEC_control> Enter (handle=0x8fa0d9a0, id=0, params=0x8fe07cb4, status=0x8fe07cc4
[DSP] @3,261,041tk: [+5 T:0x8fa0da1c] CV - VISA_enter(visa=0x8fa0d9a0): algHandle = 0x8fa0d9c8
[DSP] @3,261,116tk: [+0 T:0x8fa0da1c] ti.sdo.ce.alg.Algorithm - Algorithm_activate> Enter(handle=0x8fa0d9c8)
[DSP] @3,261,195tk: [+0 T:0x8fa0da1c] ti.sdo.fc.dskt2 - DSKT2_activateAlg> Enter (scratchId=0, alg=0x88000680)
[DSP] @3,261,278tk: [+4 T:0x8fa0da1c] ti.sdo.fc.dskt2 - DSKT2_activateAlg> Real deactivation of algorithm 0x88000610
[DSP] @3,261,361tk: [+0 T:0x8fa0da1c] ti.sdo.ce.examples.codecs.videnc_copy - VIDENCCOPY_TI_deactivate(0x88000610)
[DSP] @3,261,445tk: [+0 T:0x8fa0da1c] ti.sdo.fc.dskt2 - DSKT2_activateAlg> Exit
[DSP] @3,261,502tk: [+0 T:0x8fa0da1c] ti.sdo.ce.alg.Algorithm - Algorithm_activate> return
[DSP] @3,261,568tk: [+0 T:0x8fa0da1c] ti.sdo.ce.examples.codecs.viddec_copy - VIDDECCOPY_TI_control(0x88000680, 0x8fe07cb4, 0x10000, 0x8fa0da1c)
[DSP] @3,261,678tk: [+5 T:0x8fa0da1c] CV - VISA_exit(visa=0x8fa0d9a0): algHandle = 0x8fa0d9c8
[DSP] @3,261,751tk: [+0 T:0x8fa0da1c] ti.sdo.ce.alg.Algorithm - Algorithm_deactivate> Enter(handle=0x8fa0d9c8)
[DSP] @3,261,830tk: [+0 T:0x8fa0da1c] ti.sdo.fc.dskt2 - DSKT2_deactivateAlg> Enter (scratchId=0, algHandle=0x88000680)
[DSP] @3,261,916tk: [+4 T:0x8fa0da1c] ti.sdo.fc.dskt2 - DSKT2_deactivateAlg> Lazy deactivate of algorithm 0x88000680
[DSP] @3,262,001tk: [+0 T:0x8fa0da1c] ti.sdo.fc.dskt2 - DSKT2_deactivateAlg> Exit
[DSP] @3,262,059tk: [+0 T:0x8fa0da1c] ti.sdo.ce.alg.Algorithm - Algorithm_deactivate> return
[DSP] @3,262,125tk: [+0 T:0x8fa0da1c] ti.sdo.ce.video.VIDDEC - VIDDEC_control> Exit (handle=0x8fa0d9a0, retVal=0x0)
[DSP] @3,262,210tk: [+5 T:0x8fa0da1c] CN - NODE> returned from call(algHandle=0x8fa0d9a0, msg=0x8fe07c80); messageId=0x0003e6d2
@9,276,518us: [+0 T:0x4003a6e8] CV - VISA_call Completed: messageId=0x0003e6d2, command=0x1, return(status=0)
@9,276,650us: [+5 T:0x4003a6e8] CV - VISA_freeMsg(0x32b00, 0x4115bc80): Freeing message with messageId=0x0003e6d2
@9,276,750us: [+0 T:0x4003a6e8] ti.sdo.ce.video.VIDDEC - VIDDEC_control> Exit (handle=0x32b00, retVal=0x0)
@9,276,867us: [+5 T:0x4003a6e8] OM - Memory_dumpKnownContigBufsList> following buffers were translated/registered:
@9,276,941us: [+5 T:0x4003a6e8] OM -     [ virt: 0x411cb000, size: 00002048, phys: 0x87fff000 ]
@9,277,025us: [+5 T:0x4003a6e8] OM -     [ virt: 0x411ca000, size: 00002048, phys: 0x87ffe000 ]
@9,277,108us: [+5 T:0x4003a6e8] OM -     [ virt: 0x411c9000, size: 00002048, phys: 0x87ffd000 ]
App-> Processing frame 0...
@9,278,338us: [+0 T:0x4003a6e8] ti.sdo.ce.video.VIDENC - VIDENC_process> Enter (handle=0x32a70, inBufs=0xbefffc70, outBufs=0xbefffc60, inArgs=0xbefffabc, outArgs=0xbefffbc0)
@9,278,505us: [+5 T:0x4003a6e8] CV - VISA_allocMsg> Allocating message for messageId=0x0002fed8
@9,278,618us: [+0 T:0x4003a6e8] CV - VISA_call(visa=0x32a70, msg=0x4115ac80): messageId=0x0002fed8, command=0x0
[DSP] @3,279,577tk: [+5 T:0x8fa0c8b4] CN - NODE> 0x8fa0c780(videnc_copy#0) call(algHandle=0x8fa0c838, msg=0x8fe06c80); messageId=0x0002fed8
[DSP] @3,279,695tk: [+0 T:0x8fa0c8b4] OM - Memory_cacheInv> Enter(addr=0x87ffd000, sizeInBytes=2048)
[DSP] @3,279,775tk: [+0 T:0x8fa0c8b4] OM - Memory_cacheInv> return
[DSP] @3,279,826tk: [+0 T:0x8fa0c8b4] OM - Memory_cacheInv> Enter(addr=0x87ffe000, sizeInBytes=2048)
[DSP] @3,279,904tk: [+0 T:0x8fa0c8b4] OM - Memory_cacheInv> return
[DSP] @3,279,961tk: [+0 T:0x8fa0c8b4] ti.sdo.ce.video.VIDENC - VIDENC_process> Enter (handle=0x8fa0c838, inBufs=0x8fa0d890, outBufs=0x8fa0d89c, inArgs=0x8fe06db8, outArgs=0x8fe06dbc)
[DSP] @3,280,100tk: [+5 T:0x8fa0c8b4] CV - VISA_enter(visa=0x8fa0c838): algHandle = 0x8fa0c860
[DSP] @3,280,173tk: [+0 T:0x8fa0c8b4] ti.sdo.ce.alg.Algorithm - Algorithm_activate> Enter(handle=0x8fa0c860)
[DSP] @3,280,253tk: [+0 T:0x8fa0c8b4] ti.sdo.fc.dskt2 - DSKT2_activateAlg> Enter (scratchId=0, alg=0x88000610)
[DSP] @3,280,337tk: [+4 T:0x8fa0c8b4] ti.sdo.fc.dskt2 - DSKT2_activateAlg> Real deactivation of algorithm 0x88000680
[DSP] @3,280,422tk: [+4 T:0x8fa0c8b4] ti.sdo.fc.dskt2 - DSKT2_activateAlg> Real activation of algorithm 0x88000610
[DSP] @3,280,504tk: [+0 T:0x8fa0c8b4] ti.sdo.ce.examples.codecs.videnc_copy - VIDENCCOPY_TI_activate(0x88000610)
[DSP] @3,280,584tk: [+0 T:0x8fa0c8b4] ti.sdo.fc.dskt2 - DSKT2_activateAlg> Exit
[DSP] @3,280,642tk: [+0 T:0x8fa0c8b4] ti.sdo.ce.alg.Algorithm - Algorithm_activate> return
[DSP] @3,280,708tk: [+0 T:0x8fa0c8b4] ti.sdo.ce.examples.codecs.videnc_copy - VIDENCCOPY_TI_process(0x88000610, 0x8fa0d890, 0x8fa0d89c, 0x8fe06db8, 0x8fe06dbc)
[DSP] @3,280,830tk: [+2 T:0x8fa0c8b4] ti.sdo.ce.examples.codecs.videnc_copy - VIDENCCOPY_TI_process> memcpy (0x87ffe000, 0x87ffd000, 2048)
[DSP] @3,280,972tk: [+5 T:0x8fa0c8b4] CV - VISA_exit(visa=0x8fa0c838): algHandle = 0x8fa0c860
[DSP] @3,281,044tk: [+0 T:0x8fa0c8b4] ti.sdo.ce.alg.Algorithm - Algorithm_deactivate> Enter(handle=0x8fa0c860)
[DSP] @3,281,123tk: [+0 T:0x8fa0c8b4] ti.sdo.fc.dskt2 - DSKT2_deactivateAlg> Enter (scratchId=0, algHandle=0x88000610)
[DSP] @3,281,210tk: [+4 T:0x8fa0c8b4] ti.sdo.fc.dskt2 - DSKT2_deactivateAlg> Lazy deactivate of algorithm 0x88000610
[DSP] @3,281,296tk: [+0 T:0x8fa0c8b4] ti.sdo.fc.dskt2 - DSKT2_deactivateAlg> Exit
[DSP] @3,281,354tk: [+0 T:0x8fa0c8b4] ti.sdo.ce.alg.Algorithm - Algorithm_deactivate> return
[DSP] @3,281,419tk: [+0 T:0x8fa0c8b4] ti.sdo.ce.video.VIDENC - VIDENC_process> Exit (handle=0x8fa0c838, retVal=0x0)
[DSP] @3,281,504tk: [+0 T:0x8fa0c8b4] OM - Memory_cacheWb> Enter(addr=0x87ffe000, sizeInBytes=2048)
[DSP] @3,281,593tk: [+0 T:0x8fa0c8b4] OM - Memory_cacheWb> return
[DSP] @3,281,641tk: [+5 T:0x8fa0c8b4] CN - NODE> returned from call(algHandle=0x8fa0c838, msg=0x8fe06c80); messageId=0x0002fed8
@9,619,562us: [+0 T:0x4003a6e8] CV - VISA_call Completed: messageId=0x0002fed8, command=0x0, return(status=0)
@9,619,712us: [+5 T:0x4003a6e8] CV - VISA_freeMsg(0x32a70, 0x4115ac80): Freeing message with messageId=0x0002fed8
@9,619,816us: [+0 T:0x4003a6e8] ti.sdo.ce.video.VIDENC - VIDENC_process> Exit (handle=0x32a70, retVal=0x0)
@9,619,903us: [+0 T:0x4003a6e8] ti.sdo.ce.video.VIDDEC - VIDDEC_process> Enter (handle=0x32b00, inBufs=0xbefffc70, outBufs=0xbefffc60, inArgs=0xbefffc50, outArgs=0xbefffbb0)
@9,620,006us: [+5 T:0x4003a6e8] CV - VISA_allocMsg> Allocating message for messageId=0x0003e6d3
@9,620,103us: [+0 T:0x4003a6e8] CV - VISA_call(visa=0x32b00, msg=0x4115bc80): messageId=0x0003e6d3, command=0x0

--------------------------------------------------------------------------------------------------------------------------
Filename: ======== video_copy.cfg ========
/*
 *  Copyright 2008 by Texas Instruments Incorporated.
 *
 *  All rights reserved. Property of Texas Instruments Incorporated.
 *  Restricted rights to use, duplicate or disclose this code are
 *  granted through contract.
 *
 */

/*
 *  ======== video_copy.cfg ========
 *
 *  For details about the packages and configuration parameters used throughout
 *  this config script, see the Codec Engine Configuration Guide (link
 *  provided in the release notes).
 */

/*
 *  Configure CE's OSAL.  This codec server only builds for the BIOS-side of
 *  a heterogeneous system, so use the "DSPLINK_BIOS" configuration.
 */
var osalGlobal = xdc.useModule('ti.sdo.ce.osal.Global');
osalGlobal.runtimeEnv = osalGlobal.DSPLINK_BIOS;

/* configure default memory seg id to BIOS-defined "DDR2" */
osalGlobal.defaultMemSegId = "DDR2";

/* activate BIOS logging module */
var LogServer = xdc.useModule('ti.sdo.ce.bioslog.LogServer');

/*
 *  "Use" the various codec modules; i.e., implementation of codecs.
 *  All these "xdc.useModule" commands provide a handle to the codecs,
 *  which we'll use below to add them to the Server.algs array.
 */
var VIDDEC_COPY =
    xdc.useModule('ti.sdo.ce.examples.codecs.viddec_copy.VIDDEC_COPY');
    /*VIDDEC_COPY.codeSection = 'DDR2';
    VIDDEC_COPY.udataSection = 'DDR2';
    VIDDEC_COPY.dataSection = 'DDR2';*/
   
   
var VIDENC_COPY =
   xdc.useModule('ti.sdo.ce.examples.codecs.videnc_copy.VIDENC_COPY');
  

/*
 *  ======== Server Configuration ========
 */
var Server = xdc.useModule('ti.sdo.ce.Server');

/* The server's stackSize */
Server.threadAttrs.stackSize = 32768; //2048;

/* The servers execution priority */
Server.threadAttrs.priority = Server.MINPRI;
/*Added by Sandeep
Server.algs.codeSection = 'DDR2';
server.algs.udataSection = 'DDR2';
Server.algs.dataSection = 'DDR2'; */
//Server.traceBufferSize = 20000; //<largerSizeInBytes>;
/*
 * The array of algorithms this server can serve up.  This array also configures
 * details about the threads which will be created to run the algorithms
 * (e.g. stack sizes, priorities, etc.).
 */
Server.algs = [
    {
        name:           "viddec_copy",    // C name for the of codec
        mod:            VIDDEC_COPY,      // var VIDDEC_COPY defined above
        groupId:    0,
        threadAttrs: {
            stackSize  : 65536,       
            stackMemId: 0,                // BIOS MEM seg. ID for task's stack
            priority:   Server.MINPRI + 1 // task priority
        },
        groupId :       0,                // scratch group ID (see DSKT2 below)
    },
    {
        name:           "videnc_copy",
        mod:            VIDENC_COPY,
        groupId:    0,
        threadAttrs: {
            stackSize : 4096,//65536,
            stackMemId: 0,
            priority:   Server.MINPRI + 1
        },
        groupId :       0,
    },
];

/* we can use DMA in the VIDENC_COPY codecs */
//VIDENC_COPY.useDMA = true;

/*
 * Note that we presume this server runs on a system with DSKT2 and DMAN3,
 * so we configure those modules here.
 */


/*
 *  ======== DSKT2 (xDAIS Alg. memory allocation) configuration ========
 *
 *  DSKT2 is the memory manager for all algorithms running in the system,
 *  granting them persistent and temporary ("scratch") internal and external
 *  memory. We configure it here to define its memory allocation policy.
 *
 *  DSKT2 settings are critical for algorithm performance.
 *
 *  First we assign various types of algorithm internal memory (DARAM0..2,
 *  SARAM0..2,IPROG, which are all the same on a C64+ DSP) to "L1DHEAP"
 *  defined in the .tcf file as an internal memory heap. (For instance, if
 *  an algorithm asks for 5K of DARAM1 memory, DSKT2 will allocate 5K from
 *  L1DHEAP, if available, and give it to the algorithm; if the 5K is not
 *  available in the L1DHEAP, that algorithm's creation will fail.)
 *
 *  The remaining segments we point to the "DDRALGHEAP" external memory segment
 *  (also defined in the.tcf) except for DSKT2_HEAP which stores DSKT2's
 *  internal dynamically allocated objects, which must be preserved even if
 *  no codec instances are running, so we place them in "DDR2" memory segment
 *  with the rest of system code and static data.
 */
var DSKT2 = xdc.useModule('ti.sdo.fc.dskt2.DSKT2');
DSKT2.DARAM0     = "DDRALGHEAP";//"L1DHEAP";
DSKT2.DARAM1     = "DDRALGHEAP";//"L1DHEAP";
DSKT2.DARAM2     = "DDRALGHEAP";//"L1DHEAP";
DSKT2.SARAM0     = "DDRALGHEAP";//"L1DHEAP";
DSKT2.SARAM1     = "DDRALGHEAP";//"L1DHEAP";
DSKT2.SARAM2     = "DDRALGHEAP"; //"L1DHEAP";
DSKT2.ESDATA     = "DDRALGHEAP";
DSKT2.IPROG      = "L1DHEAP";
DSKT2.EPROG      = "DDRALGHEAP";
DSKT2.DSKT2_HEAP = "DDRALGHEAP";     //    "DDR2";

//TRACEUTIL_DSP0TRACEMASK="ti.sdo.fc.dskt2=01234567",
DSKT2.trace = true;//Added ny Sandeep.
DSKT2.debug=true; //Added ny Sandeep.
/*
 *  Next we define how to fulfill algorithms' requests for fast ("scratch")
 *  internal memory allocation; "scratch" is an area an algorithm writes to
 *  while it processes a frame of data and
 *
 *  First we turn off the switch that allows the DSKT2 algorithm memory manager
 *  to give to an algorithm external memory for scratch if the system has run
 *  out of internal memory. In that case, if an algorithm fails to get its
 *  requested scratch memory, it will fail at creation rather than proceed to
 *  run at poor performance. (If your algorithms fail to create, you may try
 *  changing this value to "true" just to get it running and optimize other
 *  scratch settings later.)
 *
 *  Next we set "algorithm scratch sizes", a scheme we use to minimize internal
 *  memory resources for algorithms' scratch memory allocation. Algorithms that
 *  belong to the same "scratch group ID" -- field "groupId" in the algorithm's
 *  Server.algs entry above, reflecting the priority of the task running the
 *  algorithm -- don't run at the same time and thus can share the same
 *  scratch area. When creating the first algorithm in a given "scratch group"
 *  (between 0 and 19), a shared scratch area for that groupId is created with
 *  a size equal to SARAM_SCRATCH_SIZES[<alg's groupId>] below -- unless the
 *  algorithm requests more than that number, in which case the size will be
 *  what the algorithm asks for. So SARAM_SCRATCH_SIZES[<alg's groupId>] size is
 *  more of a groupId size guideline -- if the algorithm needs more it will get
 *  it, but getting these size guidelines right is important for optimal use of
 *  internal memory. The reason for this is that if an algorithm comes along
 *  that needs more scratch memory than its groupId scratch area's size, it
 *  will get that memory allocated separately, without sharing.
 *
 *  This DSKT2.SARAM_SCRATCH_SIZES[<groupId>] does not mean it is a scratch size
 *  that will be automatically allocated for the group <groupId> at system
 *  startup, but only that is a preferred minimum scratch size to use for the
 *  first algorithm that gets created in the <groupId> group, if any.
 *
 *  (An example: if algorithms A and B with the same groupId = 0 require 10K and
 *  20K of scratch, and if SARAM_SCRATCH_SIZES[0] is 0, if A gets created first
 *  DSKT2 allocates a shared scratch area for group 0 of size 10K, as A needs.
 *  If then B gets to be created, the 20K scratch area it gets will not be
 *  shared with A's -- or anyone else's; the total internal memory use will be
 *  30K. By contrast, if B gets created first, a 20K shared scratch will be
 *  allocated, and when A comes along, it will get its 10K from the existing
 *  group 0's 20K area. To eliminate such surprises, we set
 *  SARAM_SCRATCH_SIZES[0] to 20K and always spend exactly 20K on A and B's
 *  shared needs -- independent of their creation order. Not only do we save 10K
 *  of precious internal memory, but we avoid the possibility that B can't be
 *  created because less than 20K was available in the DSKT2 internal heaps.)
 *
 *  In our example below, we set the size of groupId 0 to 32K -- as an example,
 *  even though our codecs don't use it.
 *
 *  Finally, note that if the codecs correctly implement the
 *  ti.sdo.ce.ICodec.getDaramScratchSize() and .getSaramScratchSize() methods,
 *  this scratch size configuration can be autogenerated by
 *  configuring Server.autoGenScratchSizeArrays = true.
 */
DSKT2.ALLOW_EXTERNAL_SCRATCH = true;
//DSKT2.SARAM_SCRATCH_SIZES[0] = 32*1024;//Commented by Sandeep
DSKT2.SARAM_SCRATCH_SIZES[0] = 600*1024;//Added by Sandeep
DSKT2.DARAM_SCRATCH_SIZES[0] = 600*1024;//Added by Sandeep
/*
 *  ======== DMAN3 (DMA manager) configuration ========
 */
var DMAN3 = xdc.useModule('ti.sdo.fc.dman3.DMAN3');

/*  First we configure how DMAN3 handles memory allocations:
 *
 *  Essentially the configuration below should work for most codec combinations.
 *  If it doesn't work for yours -- meaning an algorithm fails to create due
 *  to insufficient internal memory -- try the alternative (commented out
 *  line that assigns "DDRALGHEAP" to DMAN3.heapInternal).
 *
 *  What follows is an FYI -- an explanation for what the alternative would do:
 *
 *  When we use an external memory segment (DDRALGHEAP) for DMAN3 internal
 *  segment, we force algorithms to use external memory for what they think is
 *  internal memory -- we do this in a memory-constrained environment
 *  where all internal memory is used by cache and/or algorithm scratch
 *  memory, pessimistically assuming that if DMAN3 uses any internal memory,
 *  other components (algorithms) will not get the internal memory they need.
 *
 *  This setting would affect performance very lightly.
 *
 *  By setting DMAN3.heapInternal = <external-heap>  DMAN3 *may not* supply
 *  ACPY3_PROTOCOL IDMA3 channels the protocol required internal memory for
 *  IDMA3 channel 'env' memory. To deal with this catch-22 situation we
 *  configure DMAN3 with hook-functions to obtain internal-scratch memory
 *  from the shared scratch pool for the associated algorithm's
 *  scratch-group (i.e. it first tries to get the internal scratch memory
 *  from DSKT2 shared allocation pool, hoping there is enough extra memory
 *  in the shared pool, if that doesn't work it will try persistent
 *  allocation from DMAN3.internalHeap).
 */
//DMAN3.heapInternal    = "L1DHEAP";       /* L1DHEAP is an internal segment */
DMAN3.heapInternal = "DDRALGHEAP";    /* DDRALGHEAP is an external segment */
DMAN3.heapExternal    = "DDRALGHEAP";
DMAN3.idma3Internal   = false;
DMAN3.scratchAllocFxn = "DSKT2_allocScratch";
DMAN3.scratchFreeFxn  = "DSKT2_freeScratch";
DMAN3.debug=true;   //Added by Sandeep
/*  Next, we configure all the physical resources that DMAN3 is granted
 *  exclusively. These settings are optimized for the DSP on DM6446 (DaVinci).
 *
 *  We assume PaRams 0..79 are taken by the Arm drivers, so we reserve
 *  all the rest, up to 127 (there are 128 PaRam sets on DM6446).
 *  DMAN3 takes TCC's 32 through 63 (hence the High TCC mask is 0xFFFFFFFF
 *  and the Low TCC mask is 0). Of the 48 PaRams we reserved, we assign
 *  all of them to scratch group 0; similarly, of the 32 TCCs we reserved,
 *  we assign all of them to scratch group 0.
 *
 *  If we had more scratch groups with algorithms that require EDMA, we would
 *  split those 48 PaRams and 32 TCCs appropriately. For example, if we had
 *  a video encoder alg. in group 0 and video decoder alg. in group 1, and they
 *  both needed a number of EDMA channels, we could assing 24 PaRams and 16
 *  TCCs to Groups [0] and [1] each. (Assuming both algorithms needed no more
 *  than 24 channels to run properly.)
 */
DMAN3.paRamBaseIndex     = 80;  // 1st EDMA3 PaRAM set available for DMAN3
DMAN3.numQdmaChannels    = 8;   // number of device's QDMA channels to use
DMAN3.qdmaChannels       = [0,1,2,3,4,5,6,7]; // choice of QDMA channels to use
DMAN3.numPaRamEntries    = 48;  // number of PaRAM sets exclusively used by DMAN
DMAN3.numPaRamGroup[0]   = 48;  // number of PaRAM sets for scratch group 0
DMAN3.numTccGroup[0]     = 32;  // number of TCCs assigned to scratch group 0
DMAN3.tccAllocationMaskL = 0;   // bit mask indicating which TCCs 0..31 to use
DMAN3.tccAllocationMaskH = 0xffffffff; // assign all TCCs 32..63 for DMAN

/*  The remaining DMAN3 configuration settings are as defined in ti.sdo.fc.DMAN3
 *  defaults. You may need to override them to add more QDMA channels and
 *  configure per-scratch-group resource sub-allocations.
 */
/*
 *  @(#) ti.sdo.ce.examples.servers.video_copy.evmDM6446; 1, 0, 0,55; 1-14-2008 09:54:58; /db/atree/library/trees/ce-g30x/src/
 */


----------------------------------------------------------------------------------------------------------------------------------------
Filename:video_copy.tcf

/*
 *  Copyright 2007
 *  Texas Instruments Incorporated
 *
 *  All rights reserved.  Property of Texas Instruments Incorporated
 *  Restricted rights to use, duplicate or disclose this code are
 *  granted through contract.
 *
 */

var platform = environment["config.platform"];
print("platform   = " + platform);


/*
 * Setup platform-specific memory map:
 */
var mem_ext = [
{
    comment:    "DDRALGHEAP: off-chip memory for dynamic algmem allocation",
    name:       "DDRALGHEAP",
    base:       0x88000000,   // 128MB
    len:        0x07A00000,   // 122MB
    space:      "code/data"
},
{
    comment:    "L1DSRAM: memory for dynamic algmem allocation",
    name:       "L1DSRAM",
    base:       0x11F04000,   //
    len:        0x10000,   // 64k
    space:      "data"
},
{
    comment:    "DDR2: off-chip memory for application code and data",
    name:       "DDR2",
    base:       0x8FA00000,   // 250MB
    //len:        0x003FFFFC,
    len:        0x00400000,   //   4MB
    space:      "code/data"
},
{
    comment:    "DSPLINK: off-chip memory reserved for DSPLINK code and data",
    name:       "DSPLINKMEM",
    base:       0x8FE00000,   // 254MB
    len:        0x00100000,   //   1MB
    space:      "code/data"
},
{
    comment:    "RESET_VECTOR: off-chip memory for the reset vector table",
    name:       "RESET_VECTOR",
    base:       0x8FF00000,
    len:        0x00000080,
    space:      "code/data"
},
];


/*
 *  Internal memory partitioning for DM6446
 *
 *  On the left in the diagram below is the layout of internal memory
 *  available on DM6446 for data caching and as RAM; on the right is the
 *  diagram showing how this configuration file partitions the available
 *  64k+80k of memory. (The 32K for program cache is not affected by this
 *  configuration, and not shown below.) Please find more specifics on how
 *  the configuration is done further below.
 *
 *
 *  Physical internal memory on DM6446     Default partitioning in this .tcf
 *
 *              |//////////|                           |//////////|
 *  0x11800000  +----------+               0x11800000  +----------+
 *              | L2Cache  |                           |          |
 *              |  and/or  | 64k                       | L2 Cache | 64k
 *              |  IRAM    |                           |          |
 *              |          |                           |          |
 *  0x11810000  +----------+               0x11810000  +----------+
 *              |//////////|                           |//////////|
 *              :          :                           :          :
 *              |//////////|                           |//////////|
 *  0x11F04000  +----------+               0x11F04000  +----------+
 *              |          |                           |          |
 *              | L1DSRAM  | 48k                       | L1DSRAM  |
 *              |          |                           |          | 64k
 *  0x11F10000  +- - - - - +                           |          |
 *              |L1Cache or| 32k                       +- - - - - +
 *              |more L1DSR|               0x11F14000  | L1 cache | 16k
 *  0x11F18000  +----------+               0x11F18000  +----------+
 *              |//////////|                           |//////////|
 */

/*
 *  Specify the L2 CACHE memory setting. This value indicates how the physical
 *  internal memory of size 64K starting at 0x11800000 will be split between
 *  L2 cache and a general-purpose internal memory segment IRAM. The options
 *  are:
 *  l2Mode: "0k"  -- IRAM is 64K long, starts at 0x11800000; no L2 cache
 *  l2Mode: "32k" -- IRAM is 32K long, starts at 0x11800000; L2 cache is
 *                           32K long, starts at 0x11808000
 *  l2Mode: "64k" -- no IRAM; L2 cache is 64k long, starts at 0x11800000
 */

    var device_regs = {
        l2Mode: "64k"
    };

    var params = {
        clockRate: 594,
        catalogName: "ti.catalog.c6000",
        deviceName: "DM6446",
        regs: device_regs,
        mem: mem_ext
    };

/*
 * Now customize the generic platform with parameters specified above.
 */
utils.loadPlatform("ti.platforms.generic", params);

/*  ===========================================================================
 *  Enable heaps and tasks
 *  ===========================================================================
 */
bios.enableMemoryHeaps(prog);
bios.enableTskManager(prog);

/*  ===========================================================================
 *  Configure L1 cache and L1DSRAM segment - DM6446
 *
 *  In addition to the 64K at address 0x11800000, the DM6446 device has another
 *  48K of physical memory at 0x11F04000 available as internal RAM,
 *  called the "L1DSRAM" segment in BIOS, and it has another adjacent 32K
 *  at 0x11F10000 that can either be used entirely for L1 cache,
 *  or split between L1 cache and more internal memory.
 *
 *  The 80K segment (48K + 32K) starts at 0x11F04000. When powered on, the
 *  device uses the upper 32K for L1 cache entirely, so BIOS by default defines
 *  the L1DSRAM segment to be 48K long and does not change the cache.
 *
 *  We can change the default behavior, by shrinking the L1 cache and adding
 *  the extra space to L1DSRAM. We can set the L1 cache to be 32K (the default)
 *  or 16K, 8K, 4K, or 0K. The corresponding L1DSRAM sizes then are 48K (the
 *  default), or 64K, 72K, 76K, or 80K.
 *
 *  The L1DSRAM segment always starts at 0x11F04000.
 *  ===========================================================================
 */
    prog.module("GBL").C64PLUSCONFIGURE   = true;

    prog.module("GBL").C64PLUSL1DCFG = "16k";  // changed from default of 32k

    /*  increase the size of the L1DSRAM by 16K because L1 Cache size has been
     *  reduced by 16K
     */
    bios.L1DSRAM.len  += 0x4000;

/*  ===========================================================================
 *  Create heaps in memory segments that are to have heap
 *  ===========================================================================
 */
bios.DDR2.createHeap = true;
bios.DDR2.heapSize   = 0x20000; //K     //0x20000; // 128K

bios.DDRALGHEAP.createHeap = true;
bios.DDRALGHEAP.heapSize   = bios.DDRALGHEAP.len;

bios.L1DSRAM.createHeap       = true;
bios.L1DSRAM.enableHeapLabel  = true;
bios.L1DSRAM["heapLabel"]     = prog.extern("L1DHEAP");

bios.L1DSRAM.heapSize     = 0x10000;  // all of L1DSRAM's 64K for this heap


/*  ===========================================================================
 *  GBL
 *  ===========================================================================
 */
/* set MAR register to cache external memory 0x80000000-0x8FFFFFFF */
prog.module("GBL").C64PLUSMAR128to159 = 0x0000ffff;

prog.module("GBL").ENABLEALLTRC    = false;
prog.module("GBL").PROCID          = 0;

/*  ===========================================================================
 *  MEM : startup and SWI stack size
 *  ===========================================================================
 */
 //prog.module("MEM").STACKSEG = bios.DDR2;
prog.module("MEM").STACKSIZE =0x2000;  //            //0x1000;Modified by Sandeep

/*  ===========================================================================
 *  Global Settings
 *  ===========================================================================
 */
prog.module("MEM").ARGSSIZE = 256;

/*  ===========================================================================
 *  Enable MSGQ and POOL Managers
 *  ===========================================================================
 */
bios.MSGQ.ENABLEMSGQ = true;
bios.POOL.ENABLEPOOL = true;

/*  ===========================================================================
 *  Set all code and data sections to use DDR2
 *  ===========================================================================
 */
bios.setMemCodeSections (prog, bios.DDR2);
bios.setMemDataNoHeapSections (prog, bios.DDR2);
bios.setMemDataHeapSections   (prog, bios.DDR2);     //(prog, bios.DDR2);

/*  ===========================================================================
 *  MEM : Global
 *  ===========================================================================
 */
prog.module("MEM").BIOSOBJSEG = bios.DDR2;
prog.module("MEM").MALLOCSEG  = bios.DDRALGHEAP;

/*  ===========================================================================
 *  TSK : Global
 *  ===========================================================================
 */
prog.module("TSK").STACKSEG = bios.DDR2;
bios.TSK.STACKSIZE = 0x1000;
/*  ===========================================================================
 *  Generate configuration files...
 *  ===========================================================================
 */
if (config.hasReportedError == false) {
    prog.gen();
}
--------------------------------------------------------------------------------------------------------------------------
 
 
Many Thanks,
Sandeep.Yedire
 

 

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