DM385: Maximum VIP capture width in 8 bit mode with discrete sync/CSI 4 lane

Hi,

Are you capturing from VIP or CSI?

VIP can support at max 165MHz pixel clock on each port? Can you please check if pixel clock is below this limit?

Are you enabling any other module in the VIP pipeline? VIP will be able to capture it only if all other modules are disabled in the pipeline..

Rgds,

Brijesh

Hi, Brijesh.

I have experience with capturing through CSI, but now I need to capture wide frames through VIP. 

1) If I will capture directly to memory without chroma downsampling/resizing what will be frame width maximum?  The clock is below 165 MHz.

2) If I will use modules what is maximum frame width? 1920 or 2048?

Thank You.

P.S. And what about frame rate fall in case of CSI?

Hi Dmitry,


The max line size with CHR_DS/SC module is 1920 and without these modules, it can capture upto 4095.
Are you seeing any overflows when full frame size is set in sensor? or are you seeing any drop frame count in the capture stats?
Without this, fps should not have reduced..

Rgds,
Brijesh

Hi Brijesh,

4095 - is it in bytes or pixels? If I am capturing YUV422?

I am using IPNC RDK 3.8.0. With oscilloscope I see that AR0330 gives 30 fps(and this frame rate is set in registers).

From statistics I don't see any overflow but I see Camera Link framerate

[m3vpss ]  ==================== CameraLink_PrintDetails ====================

[m3vpss ]  319380: CAMERA: Fields = 7202 (fps = 22, CPU Load = 73)

[m3vpss ]  319381: CAMERA: Num Resets = 0 (Avg 0 ms per reset)

[m3vpss ]  =================================================================

The strange thing is CPU load, If I am capturing frame with width 2048, CPU Load is about 30%,  but if frame width is greater than 2048, CPU load is goes up to 97%.

Thank You.

Hi Dmitry,

It is in bytes.

This is strange. fps drop is because of the CPU load, but CPU load should not increase because of the frame width.
What other modules are running in the chain? can you please check any other module can cause CPU load to increase?
VIP driver does not care about input resolution and drivers CPU load will be constant.

Rgds,
Brijesh

Hi Brijesh,

My chain is:

Sensor -> SWOSD -> IPC Out(M3VPSS) -> IPC In(Video M3) -> ENC(Video M3) -> IPC BITS OUT(Video M3) -> IPC BITS IN(A8) -> Streaming

Again, this is about AR0330 -> CSI2 capture.
I can try to exclude SWOSD, but with resolution 2048*1536 chain can do up to 45 FPS, so I don't think it is SWOSD.

I think SWOSD uses CPU, can you please try excluding SWOSD?


Rgds.
Brijesh

I excluded SWOSD and it changed capture frame rate..
Now I can see 28 fps captured..

Frame is 2304x1536.

[m3vpss ] ==================== CameraLink_PrintDetails ====================
[m3vpss ] 507221: CAMERA: Fields = 14404 (fps = 28, CPU Load = 24)
[m3vpss ] 507222: CAMERA: Num Resets = 0 (Avg 0 ms per reset)
[m3vpss ] =================================================================

SWOSD was with transparent background, it uses some hardware blocks, it seems that with frame > 2048 performance changes dramatically..
But still it is not 30 FPS, that goes from sensor. .   And CPU load is only 24%..

So, hardware captures all frames but not all frames goes to software?

Hi Dmitry,

Can you try increasing capture link's number of output buffers?
I think it does not have sufficient buffers to run real time.

Regards,
Brijesh

Hi Brijesh,

Do I have to change memory map for this?

When I tried 2048x1536, I was able to capture/encode up to 45 Fps.

Now, with 2304*1536, when sensor does 30 fps, I can capture 28, when sensor does 40 fps, I can capture 31 but can only encode 23 in both cases.

Hi.

In fact, we have  successfully captured video with resolution 2560x720.

It was done though VIP0 PortA 8bit mode with DISCRETE SYNC ACTVID VBLK mode.

Video was captured from FPGA, frequency around 120MHz.

Scaler is off, but Chroma downsampler is on, so data is coming in SYSTEM_DF_YUV420SP_UV format and is ready for encoding.

First I was scared that VIP_PARSER_xtra_port_a has only 11 bits for describing src_width in pixels. But during board running and later during code viewing I observed that this field is never filled...

So, maximum width is still open question..

Strange, is your output resolution also 2560x720? i mean in the memory, you are writing 2560x720 YUV420 buffer .

Rgds,
Brijesh

Hi, 

Yes, I see full picture during streaming.

I didn't dump it before encoding but Stream is coming in that resolution and picture is the same what FPGA sends. 

And scaler is disabled.

We made more experiments.

We can capture 3840x1080( number of lines resricted due to memory map, not port restriction).

We tried to capture 4032x1080 and here we see that chroma down sampler is working until 3840 and after is broken.