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L2CFG register problem

Smitha Joseph
Prodigy 160 points

Other Parts Discussed in Thread: SYSBIOS

Hi,

I am building an application on c6424 evm with ccsv4 and dsp/bios 6. I have added the following code in my program to enable L2 cache of size 64k.

  UInt32* CacheRegs = (UInt32*)0x01840000 ;

 (*CacheRegs) = (*CacheRegs)| 2;

When I view the L2CFG register using register view, it is showing value as 0x0001010.  But the memory display shows 0x01840000 contains 2. From the spru871j (megamodule) document, the address of L2CFG is given as 0x01840000.

 In the .cfg file, I have given to disable cache for address 0x80000000 - 0x8FFFFFFFF

var ti_sysbios_family_c64p_Cache = xdc.useModule('ti.sysbios.family.c64p.Cache');

ti_sysbios_family_c64p_Cache.MAR128_159 = 254;

Should I do anything additional to enable L2cache?

  • 0
    TI__Mastermind 20805 points

    Joseph --

    I assume you are using CCSv4.1 and BIOS 6.21.00.13 (or similar 6.21.0x).

    If so, the best way to set up memory is to use the platform wizard and make a custom platform with specific cache sizes etc.   BIOS initialization will read the settings from this platform and enable L1 and L2 cache according to the settings you specify in the platform.   BIOS will automatically enable the MAR bits for the external memory if you do not specify the MAR settings with a statement like you have above.

    To see demo of the platform wizard, open CCSv4 help and search for "Demo of RTSC Platform ".   This will take you to a wink demo that hopefully helps you.

    We've updated the memory documentation in latest BIOS 6.30 release.   The 6.30 release is not available externally yet but you can read the memory chapter in the doc.  Most of the topics apply to 6.21.  The BIOS 6.30 User's Guide can be found here:  http://processors.wiki.ti.com/index.php/SYS/BIOS_User_Guide

    Regards,
    -Karl-