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BT 656 input to CCDC

Karthik Ram
Prodigy 180 points

Hello I am Karthik,

In the camera ISP module, it is mentioned that there is no bridging option available for BT 656 mode.

The CCDC module accepts only 16 bit data from bridge lane shifter. But the output of BT 656 mode is either 8 or 10 bit wide.

Then how it is possible for CCDC to accept BT 656 mode input.

And one more question?

How bridge lane shifting operation is performed. It is spruf98g pdf file, it is so confusing. Please explain it clearly for me.

 

Thanks in advance,

 

With regards,

Karthik

  • 0
    TI__Intellectual 1280 points

    Karthik,

    You are correct in that ITU-R BT.656 protocol (which supports YCbCr4:2:2 data over 8 or 10 bit video interface with embedded syncs) cannot be used when bridge is enabled.  You can reference Table 12-28 of OMAP35x TRM (SPRUF98F), Allowed Data Flow Through CCDC, which shows which format(s) support bridge - Sync Mode.  The bridge/data lane shifter servers 2 purposes.  Data lane shifter gives flexibility to parallel camera connection and permits dynamic reduction of pixel data (Ex: 10 bit to 8 bit) and  also handles shifting of data to least significant data lanes when fewer than 12 data lanes are used.  The bridge allows packing of bytes/8-bit data into 16 bit words (Max data rate allowed is increased when bridge is used).  As shown in Figure 12-53 of TRM, Bridge lane shifter is located before CCDC.  Table 12-27 (Data-Lane Shifter) of TRM describes how 8/10/12 bit parallel data can be shifted based on ISP_CTRL[7:6] shift register setting.  ISP_CTRL[3:2) describes how bit field controls 8 to 16 bit bridge at input of CCDC module.  Ex bridge usage...When a device is used that sends 16 bits per pixel the data is transferred through 8 data lanes at x2 pixel clock.  Bridge can be used to reassemble the 16-bits/pixel at input of CCDC.  For BT656 input mode, CCDC_CFG[5] sets data width to 8 or 10 bits and takes precendence over CCDC_SYN_MODE[13:12] and CCDC_SYN_MODE[10:8]bit fields used in sync mode operation.

  • 0 in reply to JamesJ35562
    Prodigy 180 points

    Hello James J,

    Thank you for your information.

    I need one more clarification.

    Question No.1

    It is given that CCDC module accepts only 16 bit from the bridge lane shifter. Then it how comes possible for other raw data and BT 656 mode data to enter

    the video processing block.Will other data bypass the bridge lane shifter and directly goes to CCDC initial processing block? (refer table 12.28).

     

    Question No.2

    In table 12.28 it is given that only 8/10 bits YUV 4:2:2 format, sync mode <130 MHz can only be sent through bridge lane shifter. Why?