• State TI Thinks Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 1 answer
  • Subscribers 99 subscribers
  • Views 1346 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA3: System clock and CLKOUT issue

Milan Bajza
Expert 1396 points

Part Number: TDA3

Hello,

the OSC0 is connected with a 20 MHz crystal and I need 25 MHz at CLKOUT1 output to drive a UB960 serializer. Currently I found only PLL divider for the CLKOUT. Is there an other way to get 25 MHz?

In another possible case, if I use 25 MHz at OSC1, I get 25 MHz at CLKOUT1. So it could be the best solution. Are there some disadvantages according to VSDK or other thinks? Why is the OSC1 on the EVM connected to a 22.5792 MHz crystal?

Best regards,
Milan

  • 0
    TI__Mastermind 30245 points

    Hi Milan,

    Providing a 25 MHz crystal on the OSC1 input would be a good solution to get 25 MHz on CLKOUT1. The reason why 22.5792 MHz is populated on the EVM is to support audio applications to achieve required standard audio sampling rates. 

    Vision SDK by default does not use SYSCLK2 for any of its links or applications. So you should be good.

    Thanks and Regards,

    Piyali

  • 0 in reply to Piyali Goswami
    TI__Expert 4885 points

    Hi, ,

    Just to add, you can use CTT to visualize the clock tree of the device.The CTT is available at:

    Regards,

    Mariya

  • 0 in reply to Mariya Petkova
    Expert 1396 points

    Hi Piyali and Mariya,

    thank you for your answers.

    My real goal is to use only one crystal for TDA3, UB960 and UB953 on a custom board. With one clock source, sensor-capturing and display-output work with the same base clock and clock drifting is avoided. The SerDes devices need a 25 MHz clock, provided from TDA3-CLKOUT.

    Is this possible?

    The Clock Tree Tool is a good tool, it shows dependencies of many components, clocks and clock layers. I realized that providing SYS_CLK1 is required for the TDA3. SYS_CLK2 is a secondary clock source for some modules. The TDA3 is not working with SYS_CLK2, only.

    Is it right?

    Best Regards,
    Milan

  • 0 in reply to Milan Bajza
    TI__Guru**** 479035 points

    Hi Milan,

    Why do you require to synchronize capture and display at the clock level? Typically if VSYNCs are synchronized that should be good enough.

    Could you please explain the usecase?

    Regards,

    Brijesh

  • 0 in reply to Milan Bajza
    TI__Mastermind 30245 points
    Hi Milan,

    Yes, SYS_CLK1 is a primary clock source for multiple DPLLs. Hence this is very much required.

    One option (This is in case you are not using GMAC) is to set the M2 divider of DPLL_DSP_GMAC to 40 to make the 250 MHz GMAC clock to 25 MHz. The DPLL_DSP_GMAC M2 output can be directed to the clock out mux. But if you are using GMAC, this is not a feasible solution.

    Like Brijesh suggested, it would be good to understand the usecase and requirement further.

    Thanks and Regards,
    Piyali
  • 0 in reply to Piyali Goswami
    TI__Guru**** 479035 points

    Hi Milan,

    As discussed on the call, you could use 96MHz clock from FUNC_96M_AON and get 24MHz clock on CLKOUT mux by programming 1/4 divider. You could use this 24MHz clock as reference clock input to UB960 also. 

    This FUNC_96M_AON is fixed clock, set to 96MHz always since this frequency is required for CSI-CAL and also for few peripherals.

    Regards,

    Brijesh