Tool/software: Linux
Hi：
I want to use edma for data transfer of nand flash attached to gpmc，but I find that there is no interrupt of dma generated when using original sdk of dra718，
then I find the following questions about nand configuration
1.the Capacity of nand flash I am using is 256MB，is there any question when I do not change the range of ranges property as follows with red color masked？
and what is the meaning of ranges property？
&gpmc {
/*
* For the existing IOdelay configuration via U-Boot we don't
* support NAND on dra72-evm. Keep it disabled. Enabling it
* requires a different configuration by U-Boot.
*/
status = "okay";
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
/* To use NAND, DIP switch SW5 must be set like so:
* SW5.1 (NAND_SELn) = ON (LOW)
* SW5.9 (GPMC_WPN) = OFF (HIGH)
*/
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* device IO registers */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ /* device IO registers */
ti,nand-ecc-opt = "bch8";
ti,nand-xfer-type = "prefetch-irq";
/*
ti,elm-id = <&elm>;
*/
nand-bus-width = <8>;
gpmc,device-width = <2>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <80>;
gpmc,cs-wr-off-ns = <80>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <60>;
gpmc,adv-wr-off-ns = <60>;
gpmc,we-on-ns = <10>;
gpmc,we-off-ns = <50>;
gpmc,oe-on-ns = <4>;
gpmc,oe-off-ns = <40>;
gpmc,access-ns = <40>;
gpmc,wr-access-ns = <80>;
gpmc,rd-cycle-ns = <80>;
gpmc,wr-cycle-ns = <80>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.ROOTFS";
reg = <0x00000000 0x07800000>;
};
partition@1 {
label = "NAND.LIB";
reg = <0x07800000 0x01800000>;
};
partition@2 {
label = "NAND.USR";
reg = <0x09000000 0x01000000>;
};
partition@3 {
label = "NAND.LIB_BACK";
reg = <0x0a000000 0x01800000>;
};
partition@4 {
label = "NAND.USR_BACK";
reg = <0x0b800000 0x01000000>;
};
partition@5 {
label = "NAND.FLAG";
reg = <0x0c800000 0x0600000>;
};
};
};
2.through the trm I know the dma is conneted to the pfwp module of gpmc，there is a register named GPMC_PREFETCH_STATUS within gpmc module，there is a question，can I understand as follows，
when pfwp starts to work， the bits of 【13:0】COUNTVALUE of GPMC_PREFETCH_STATUS become 0 when fpwp completes transfer from nand flash to fifo
I hope for your response as soon as possible
thanks
yan xiaoyong
