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Omap3530 SPI

Laurens
Prodigy 20 points
Other Parts Discussed in Thread: OMAP3530, TXS0108E

I am trying to make a OMAP3530 (beagleboard) communicate with a ADC using SPI (McSPI3). I have set-up the multiplexing such that CLK is configured as an input-pin. When I try to transfer data and monitor CLK I see that it does not always reach GND. For example: the first pulse is fine but the following pulses do not reach GND but their lowest level is approx 500 mV. Sometimes the third pulse is fine as well.

Does anyone know what is happening?

Edit: note that I have a level converter (TXS0108E) connected to the OMAP3530 to convert from 1.8 to 5v signals. When I have nothing connected to the other end of the level-converter, the signal seems fine.

  • 0
    TI__Mastermind 28215 points

    Laurens

     

    Just so I am sure I understand…

    The OMAP SPI3 is master, correct?

    The voltage low is measured between the OMAP and the level shifter?

    When the ADC is disconnected, the voltage drives low correctly?

     

    Since the level shifter is bi-directional, is it possible there is some contention on the line to the ADC when the ADC is connected?

      Paul

  • 0 in reply to PaulM
    Prodigy 20 points

    Indeed the OMAP SPI3 is master and the voltage low is measured between the OMAP and the level shifter.

     

    With the level shifter connected but nothing on the 'high' side i get this (yellow is in between the OMAP and level shifter):

    output3.png

    When I connect anything (even only the scope) to the 'high' side, i get this:

    output2.png and sometimes: output1.png

     

    Is the OMAP able to source/sink the current needed to drive the level shifter? (is that what might cause the voltage-shifts?). I have tried with a transistor in between the OMAP and level shifter and find that this improves the behavior somewhat, but still sometimes fails:

    output4.png

     

  • 0 in reply to Laurens
    TI__Mastermind 28215 points

    Laurens

    This still looks like some signal contention/short  on the B port of the level shifter.

    In image 2 the B Port never gets to a logic low, it's at mid voltage as if something is driving the line high while the level shifter is trying to drive a low.

    Image 4 tells the same story, The high phase of the clock for periods 5, 7, and 8 are getting squashed because something is trying to drive the signal low at the same time therefore the output of the level shifter (B port) it only making it to mid rail ~2.5v.

    Image 2 looks like the same thing.

    It actually looks like a data signal is shorted with the clock or you have have incorrect connection (ADC data o/p connected to clock from the level shifter).

      Paul