Other Parts Discussed in Thread: TPS65218
Tool/software: Linux
Hi!
I have a custom board based on AM4379 and LAN8710 Ethernet PHY connected in MII mode. I have done some modifications to u-boot from the PROCESSOR-SDK-LINUX-AM437X 04_00_00_04, but ethernet does not work at all. I can't load Linux because ethernet is not functional. However I also ported v2017.09-rc2 to the board and Ethernet works as expected, so the HW design is OK. And I used the same dts file for both u-boot versions (mainline and SDK)
What I have found so far:
1) TI SDK uses internal dtb files for pin mux. File board/ti/am43xx/mux.c is not involved, so no modifications are necessary to change pin mux
2) MII mode does not work, but MDIO works fine because I can read PHY registers
3) LAN8710 provides all necessary frequencies to CPU, but as stated before u-boot 2017-09 worked as expected.
Was MII functionality reduced or modified? If I had u-boot version used as a baseline for all modification for SDK..
I want to have SDK from TI fully functional and therefore need to figure out what is wrong with it and finally enable it for my board. I have attached the diff file for reference
U-Boot SPL 2017.01-00319-g33a324a-dirty (Sep 11 2017 - 16:14:10)
Trying to boot from MMC1
SPL: Please implement spl_start_uboot() for your board
SPL: Direct Linux boot not active!
reading u-boot.img
reading u-boot.img
reading u-boot.img
reading u-boot.img
U-Boot 2017.01-00319-g33a324a-dirty (Sep 11 2017 - 16:14:10 +0300)
CPU : AM437X-GP rev 1.2
Model: TI AM437x uSomIQ AM437x
DRAM: 512 MiB
PMIC: TPS65218
NAND: 0 MiB
MMC: OMAP SD/MMC: 0
reading uboot.env
** Unable to read "uboot.env" from mmc0:1 **
Using default environment
Net: <ethaddr> not set. Validating first E-fuse MAC
cpsw, usb_ether
Hit any key to stop autoboot: 0
=> set autoload no
=> dhcp
link up on port 0, speed 100, full duplex
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
BOOTP broadcast 5
BOOTP broadcast 6
BOOTP broadcast 7
BOOTP broadcast 8
BOOTP broadcast 9
Abort
=> mii info
PHY 0x00: OUI = 0x01F0, Model = 0x0F, Rev = 0x01, 100baseT, FDX
=> mii dump 0 0
0. (3100) -- PHY control register --
(8000:0000) 0.15 = 0 reset
(4000:0000) 0.14 = 0 loopback
(2040:2000) 0. 6,13 = b01 speed selection = 100 Mbps
(1000:1000) 0.12 = 1 A/N enable
(0800:0000) 0.11 = 0 power-down
(0400:0000) 0.10 = 0 isolate
(0200:0000) 0. 9 = 0 restart A/N
(0100:0100) 0. 8 = 1 duplex = full
(0080:0000) 0. 7 = 0 collision test enable
(003f:0000) 0. 5- 0 = 0 (reserved)
=> mii dump 0 1
1. (782d) -- PHY status register --
(8000:0000) 1.15 = 0 100BASE-T4 able
(4000:4000) 1.14 = 1 100BASE-X full duplex able
(2000:2000) 1.13 = 1 100BASE-X half duplex able
(1000:1000) 1.12 = 1 10 Mbps full duplex able
(0800:0800) 1.11 = 1 10 Mbps half duplex able
(0400:0000) 1.10 = 0 100BASE-T2 full duplex able
(0200:0000) 1. 9 = 0 100BASE-T2 half duplex able
(0100:0000) 1. 8 = 0 extended status
(0080:0000) 1. 7 = 0 (reserved)
(0040:0000) 1. 6 = 0 MF preamble suppression
(0020:0020) 1. 5 = 1 A/N complete
(0010:0000) 1. 4 = 0 remote fault
(0008:0008) 1. 3 = 1 A/N able
(0004:0004) 1. 2 = 1 link status
(0002:0000) 1. 1 = 0 jabber detect
(0001:0001) 1. 0 = 1 extended capabilities
=> mii dump 0 2
2. (0007) -- PHY ID 1 register --
(ffff:0007) 2.15- 0 = 7 OUI portion
Here is how u-boot 2017.09 boots:
U-Boot SPL 2017.09-rc2-dirty (Sep 07 2017 - 12:45:08)
Trying to boot from MMC1
SPL: Please implement spl_start_uboot() for your board
SPL: Direct Linux boot not active!
reading u-boot.img
reading u-boot.img
reading u-boot.img
reading u-boot.img
U-Boot 2017.09-rc2-dirty (Sep 07 2017 - 12:45:08 +0300)
CPU : AM437X-GP rev 1.2
Model: TI AM437x uSomIQ AM437x
DRAM: 512 MiB
PMIC: TPS65218
NAND: 0 MiB
MMC: OMAP SD/MMC: 0
reading uboot.env
** Unable to read "uboot.env" from mmc0:1 **
Using default environment
Net: CACHE: Misaligned operation at range [9df1bf80, 9df1c024]
Warning: ethernet@4a100000 using MAC address from ROM
eth0: ethernet@4a100000
Hit any key to stop autoboot: 0
=> set autoload no
=> dhcp
link up on port 0, speed 100, full duplex
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
DHCP client bound to address 192.168.1.103 (2509 ms)
=>
diff -ubNr a/arch/arm/dts/am437x-usomiq.dts b/arch/arm/dts/am437x-usomiq.dts
--- a/arch/arm/dts/am437x-usomiq.dts 1970-01-01 03:00:00.000000000 +0300
+++ b/arch/arm/dts/am437x-usomiq.dts 2017-09-11 14:07:39.654386544 +0300
@@ -0,0 +1,410 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* AM437x SK EVM */
+
+/dts-v1/;
+
+#include "am4372.dtsi"
+#include <dt-bindings/pinctrl/am43xx.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "TI AM437x uSomIQ AM437x";
+ compatible = "ti,am437x-usomiq","ti,am437x-sk-evm","ti,am4372","ti,am43";
+
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer2;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_pins>;
+
+ led@0 {
+ label = "am437x-sk:red:heartbeat";
+ gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led@1 {
+ label = "am437x-sk:green:mmc1";
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ led@2 {
+ label = "am437x-sk:blue:cpu0";
+ gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */
+ linux,default-trigger = "cpu0";
+ default-state = "off";
+ };
+
+ led@3 {
+ label = "am437x-sk:blue:usr3";
+ gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */
+ default-state = "off";
+ };
+ };
+};
+
+&am43xx_pinmux {
+ leds_pins: leds_pins {
+ pinctrl-single,pins = <
+ 0x228 (PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */
+ 0x22c (PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */
+ 0x230 (PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */
+ 0x234 (PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */
+ >;
+ };
+
+ i2c0_pins: i2c0_pins {
+ pinctrl-single,pins = <
+ 0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
+ 0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
+ >;
+ };
+
+ i2c1_pins: i2c1_pins {
+ pinctrl-single,pins = <
+ 0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
+ 0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
+ >;
+ };
+
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ 0x0f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
+ 0x0f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
+ 0x0f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
+ 0x0fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
+ 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
+ 0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
+ 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+ >;
+ };
+
+ ecap0_pins: backlight_pins {
+ pinctrl-single,pins = <
+ 0x164 (PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
+ >;
+ };
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
+ 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
+ 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
+ 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
+ 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
+ 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
+ 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
+ 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
+ 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
+ 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
+ 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
+ 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
+ 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
+ >;
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins = <
+ /* Slave 1 reset value */
+ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
+ 0x14c (PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */
+ >;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins = <
+ /* MDIO reset value */
+ 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ qspi_pins: qspi_pins {
+ pinctrl-single,pins = <
+ 0x210 (PIN_INPUT_PULLUP | MUX_MODE3) /* cam0_data2.qspi_clk */
+ 0x214 (PIN_INPUT_PULLUP | MUX_MODE3) /* cam0_data3.qspi_csn */
+ 0x218 (PIN_INPUT_PULLUP | MUX_MODE3) /* cam0_data4.qspi_d0 */
+ 0x21c (PIN_INPUT_PULLUP | MUX_MODE3) /* cam0_data5.qspi_d1 */
+ 0x220 (PIN_INPUT_PULLUP | MUX_MODE3) /* cam0_data6.qspi_d2 */
+ 0x224 (PIN_INPUT_PULLUP | MUX_MODE3) /* cam0_data7.qspi_d3 */
+ >;
+ };
+
+ usb1_pins: usb1_pins {
+ pinctrl-single,pins = <
+ 0x2c0 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
+ >;
+ };
+
+ usb2_pins: usb2_pins {
+ pinctrl-single,pins = <
+ 0x2c4 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
+ >;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ clock-frequency = <400000>;
+
+ tps@24 {
+ compatible = "ti,tps65218";
+ reg = <0x24>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ dcdc1: regulator-dcdc1 {
+ compatible = "ti,tps65218-dcdc1";
+ /* VDD_CORE limits min of OPP50 and max of OPP100 */
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <1144000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc2: regulator-dcdc2 {
+ compatible = "ti,tps65218-dcdc2";
+ /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <1378000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc3: regulator-dcdc3 {
+ compatible = "ti,tps65218-dcdc3";
+ regulator-name = "vdds_ddr";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc4: regulator-dcdc4 {
+ compatible = "ti,tps65218-dcdc4";
+ regulator-name = "v3_3d";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: regulator-ldo1 {
+ compatible = "ti,tps65218-ldo1";
+ regulator-name = "v1_8d";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ power-button {
+ compatible = "ti,tps65218-pwrbutton";
+ status = "okay";
+ interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
+ };
+ };
+
+ at24@50 {
+ compatible = "at24,24c256";
+ pagesize = <64>;
+ reg = <0x50>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <400000>;
+};
+
+&epwmss0 {
+ status = "okay";
+};
+
+&ecap0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ecap0_pins>;
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio5 {
+ status = "okay";
+};
+
+&mmc1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+
+ vmmc-supply = <&dcdc4>;
+ bus-width = <4>;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
+
+&usb2_phy1 {
+ status = "okay";
+};
+
+&usb1 {
+ dr_mode = "peripheral";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_pins>;
+};
+
+&usb2_phy2 {
+ status = "okay";
+};
+
+&usb2 {
+ dr_mode = "host";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_pins>;
+};
+
+&qspi {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qspi_pins>;
+
+ spi-max-frequency = <48000000>;
+ m25p80@0 {
+ compatible = "mx66l51235l","spi-flash";
+ spi-max-frequency = <48000000>;
+ reg = <0>;
+ spi-cpol;
+ spi-cpha;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* MTD partition table.
+ * The ROM checks the first 512KiB
+ * for a valid file to boot(XIP).
+ */
+ partition@0 {
+ label = "QSPI.U_BOOT";
+ reg = <0x00000000 0x000080000>;
+ };
+ partition@1 {
+ label = "QSPI.U_BOOT.backup";
+ reg = <0x00080000 0x00080000>;
+ };
+ partition@2 {
+ label = "QSPI.U-BOOT-SPL_OS";
+ reg = <0x00100000 0x00010000>;
+ };
+ partition@3 {
+ label = "QSPI.U_BOOT_ENV";
+ reg = <0x00110000 0x00010000>;
+ };
+ partition@4 {
+ label = "QSPI.U-BOOT-ENV.backup";
+ reg = <0x00120000 0x00010000>;
+ };
+ partition@5 {
+ label = "QSPI.KERNEL";
+ reg = <0x00130000 0x0800000>;
+ };
+ partition@6 {
+ label = "QSPI.FILESYSTEM";
+ reg = <0x00930000 0x36D0000>;
+ };
+ };
+};
+
+&mac {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cpsw_default>;
+ pinctrl-1 = <&cpsw_sleep>;
+ dual_emac = <1>;
+ status = "okay";
+};
+
+&davinci_mdio {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&davinci_mdio_default>;
+ pinctrl-1 = <&davinci_mdio_sleep>;
+ status = "okay";
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+ phy-mode = "mii";
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "mii";
+};
+
+&elm {
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
+
+&cpu {
+ cpu0-supply = <&dcdc2>;
+};
+
diff -ubNr a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
--- a/arch/arm/dts/Makefile 2017-06-29 00:44:03.000000000 +0300
+++ b/arch/arm/dts/Makefile 2017-09-11 14:06:27.992548456 +0300
@@ -124,7 +124,8 @@
am335x-rut.dtb
dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
am43x-epos-evm.dtb \
- am437x-idk-evm.dtb
+ am437x-idk-evm.dtb \
+ am437x-usomiq.dtb
dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
diff -ubNr a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
--- a/board/ti/am43xx/board.c 2017-06-29 00:44:04.000000000 +0300
+++ b/board/ti/am43xx/board.c 2017-09-11 16:34:09.275233484 +0300
@@ -184,6 +184,17 @@
.emif_sdram_config_ext = 0xc163,
};
+const struct ctrl_ioregs ioregs_ddr3_16 = {
+ .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
+ .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
+ .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
+ .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
+ .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
+ .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
+ .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
+ .emif_sdram_config_ext = 0xc163|0x20000, // for 16 bit
+};
+
const struct emif_regs ddr3_emif_regs_400Mhz = {
.sdram_config = 0x638413B2,
.ref_ctrl = 0x00000C30,
@@ -307,6 +318,32 @@
.emif_cos_config = 0x00ffffff
};
+static const struct emif_regs ddr3_usom_emif_regs_400Mhz = {
+ .sdram_config = 0x638413b2|(1<<14), /* 16bit wide */
+ .sdram_config2 = 0x00000000,
+ .ref_ctrl = 0x00000c30,
+ .sdram_tim1 = 0xeaaad4db,
+ .sdram_tim2 = 0x266b7fda,
+ .sdram_tim3 = 0x107f8678,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x50074be4,
+ .temp_alert_config = 0x0,
+ .emif_ddr_phy_ctlr_1 = 0x0e084008,
+ .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
+ .emif_ddr_ext_phy_ctrl_2 = 0x89,
+ .emif_ddr_ext_phy_ctrl_3 = 0x90,
+ .emif_ddr_ext_phy_ctrl_4 = 0x8e,
+ .emif_ddr_ext_phy_ctrl_5 = 0x8d,
+ .emif_rd_wr_lvl_rmp_win = 0x0,
+ .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x80000000,
+ .emif_prio_class_serv_map = 0x80000001,
+ .emif_connect_id_serv_1_map = 0x80000094,
+ .emif_connect_id_serv_2_map = 0x00000000,
+ .emif_cos_config = 0x000FFFFF
+};
+
void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
{
if (board_is_eposevm()) {
@@ -342,7 +379,7 @@
if (board_is_eposevm())
return &epos_evm_dpll_ddr[ind];
- else if (board_is_evm() || board_is_sk())
+ else if (board_is_evm() || board_is_sk() || board_is_usomiq())
return &gp_evm_dpll_ddr;
else if (board_is_idk())
return &idk_dpll_ddr;
@@ -538,6 +575,7 @@
RTC_BOARD_EVM12,
RTC_BOARD_GPEVM,
RTC_BOARD_SK,
+ RTC_BOARD_USOMIQ,
};
/*
@@ -568,6 +606,9 @@
case RTC_BOARD_SK:
name = "AM43__SK";
break;
+ case RTC_BOARD_USOMIQ:
+ name = "AM43USOM";
+ break;
}
ti_i2c_eeprom_am_set(name, rev);
}
@@ -584,6 +625,8 @@
return RTC_BOARD_GPEVM;
else if (board_is_sk())
return RTC_BOARD_SK;
+ else if (board_is_usomiq())
+ return RTC_BOARD_USOMIQ;
return 0;
}
@@ -615,6 +658,9 @@
} else if (board_is_idk()) {
config_ddr(400, &ioregs_ddr3, NULL, NULL,
&ddr3_idk_emif_regs_400Mhz, 0);
+ } else if (board_is_usomiq()) {
+ config_ddr(400, &ioregs_ddr3_16, NULL, NULL,
+ &ddr3_usom_emif_regs_400Mhz, 0);
}
}
#endif
@@ -816,7 +862,7 @@
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
- .phy_addr = 16,
+ .phy_addr = 0,
},
{
.slave_reg_ofs = 0x308,
@@ -901,7 +947,10 @@
eth_setenv_enetaddr("eth1addr", mac_addr);
}
#endif
- if (board_is_eposevm()) {
+ if (board_is_usomiq()) {
+ writel(MII_MODE_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
+ } else if (board_is_eposevm()) {
writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
cpsw_slaves[0].phy_addr = 16;
@@ -961,6 +1010,8 @@
return 0;
else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
return 0;
+ else if (board_is_usomiq() && !strcmp(name, "am437x-usomiq"))
+ return 0;
else
return -1;
}
diff -ubNr a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h
--- a/board/ti/am43xx/board.h 2017-06-29 00:44:04.000000000 +0300
+++ b/board/ti/am43xx/board.h 2017-09-11 14:11:47.458909406 +0300
@@ -17,6 +17,11 @@
#define DEV_ATTR_MAX_OFFSET 5
#define DEV_ATTR_MIN_OFFSET 0
+static inline int board_is_usomiq(void)
+{
+ return board_ti_is("AM43USOM");
+}
+
static inline int board_is_eposevm(void)
{
return board_ti_is("AM43EPOS");
diff -ubNr a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c
--- a/board/ti/common/board_detect.c 2017-06-29 00:44:04.000000000 +0300
+++ b/board/ti/common/board_detect.c 2017-09-11 14:19:14.645413002 +0300
@@ -152,6 +152,14 @@
return 0; /* EEPROM has already been read */
#endif
+#if 1
+ /* Ugly hack for an empty EEPROM */
+ ep->header = TI_EEPROM_HEADER_MAGIC;
+ strlcpy(ep->name, "AM43USOM", TI_EEPROM_HDR_NAME_LEN + 1);
+ ep->version[0] = 0x0;
+ ep->serial[0] = 0x0;
+ ep->config[0] = 0x0;
+#else
/* Initialize with a known bad marker for i2c fails.. */
ep->header = TI_DEAD_EEPROM_MAGIC;
ep->name[0] = 0x0;
@@ -174,6 +182,7 @@
strlcpy(ep->version, "BBG1", TI_EEPROM_HDR_REV_LEN + 1);
else
strlcpy(ep->version, am_ep.version, TI_EEPROM_HDR_REV_LEN + 1);
+#endif
ti_eeprom_string_cleanup(ep->version);
strlcpy(ep->serial, am_ep.serial, TI_EEPROM_HDR_SERIAL_LEN + 1);
ti_eeprom_string_cleanup(ep->serial);
diff -ubNr a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
--- a/configs/am43xx_evm_defconfig 2017-06-29 00:44:04.000000000 +0300
+++ b/configs/am43xx_evm_defconfig 2017-09-11 14:07:07.855345900 +0300
@@ -39,7 +39,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
+CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm am437x-usomiq"
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
diff -ubNr a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
--- a/include/configs/am43xx_evm.h 2017-06-29 00:44:04.000000000 +0300
+++ b/include/configs/am43xx_evm.h 2017-09-11 16:09:00.106945843 +0300
@@ -173,6 +173,7 @@
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
#define CONFIG_QSPI_QUAD_SUPPORT
#define CONFIG_TI_EDMA3
+#define CONFIG_SPI_FLASH_STMICRO
/* Enhance our eMMC support / experience. */
#define CONFIG_CMD_GPT
@@ -270,12 +271,14 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_NET_RETRY_COUNT 10
-#define CONFIG_PHY_GIGE
#endif
#define CONFIG_DRIVER_TI_CPSW
#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+#if 0
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
+#endif
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ETH_SUPPORT)
#undef CONFIG_ENV_IS_IN_FAT
Binary files a/lib/efi_loader/helloworld.efi and b/lib/efi_loader/helloworld.efi differ
Binary files a/lib/efi_loader/helloworld.so and b/lib/efi_loader/helloworld.so differ