• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 381 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

66AK2E05: Clocking scheme

TIDR
Genius 9355 points
Part Number: 66AK2E05


My customer is using the CDCM6208V2 (not V1 like on the EVM) to generate the clocks to 66AK2E05. However, they are pin strapping the device  and getting clocks to CORE, NETCP and DDR at 125MHz (not 100MHz) as in the EVM. This would mean that they would need to likely tweak some of the PLL setting for clock in our SDK deliverable to make it work on their boards.Is there any other issue with running these clocks at 125MHz instead of 100MHz?

Alternately the customer is considering using the CDCM HCSL outputs connected to our LVDS clock inputs. This mode would allow them to use the same 100MHz we use on our EVM.

Any comments on either approach?

Thanks!

  • 0
    TI__Guru**** 161600 points
    Hi,

    The CDCM6208V2 should work. See the CORE, NETCP & DDR CLKP/N timing requirements, all have minimal cycle time of 3.2 ns and the max cycle time is 25ns, so 125MHz clock input should be within this range.

    Also see 3.1 System PLL Clock Inputs of the Hardware Design Guide for Keystone II devices, Table 4 KeyStone II System PLL Clock Inputs. The frequency range for all of them is between 40 & 312.5 MHz.

    Of course you should consider that you would need to tweak the PLL settings.

    Best Regards,
    Yordan