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AM3352: Burst write issues with 4 devices on GPMC bus

Jarret Adam
Prodigy 75 points

Part Number: AM3352

Hi there,

Regarding the GPMC bus - looking for clarification below. We have 4 devices on the bus but the total capacitance is less than 30pF. Thanks!

“Up to 100 MHz external memory clock performance (single device)”

How should I read the above in the case when the total cap load on the GPMC is lower than 30pF:

a)       The GPMC can support 100MHz clock only when the GPMC is connected to a single device…..period; so as consequence, when two or more devices are connected to the GPMC on different #CSx (x = 0, 1, 2, 3) the maximum clock must be lower than 100MHz (50MHz respectively…) for any of the #CS.

b)      The GPMC can support 100MHz clock on a single chip select (#CS), all the other devices connected to the other #CS must be set to lower than 100 MHz (50MHz respectively…)

  • 0
    TI__Guru**** 161600 points
    I've notified the factory team . Their feedback will be posted here.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Prodigy 180 points
    Please provide updates to this issue.
  • 0 in reply to Catalin Palade
    TI__Guru**** 161600 points

    Hi Catalin,  Jarred,

    Have you noticed this

      "Although the GPMC interface can drive up to seven chip-selects, the frequency specified for this interface is for a specific load. If this load is exceeded, the maximum frequency cannot be reached. One solution is to implement a board with buffers, to allow the slowest device to maintain the total load on the lines"

    The above information suggests that if you didn't reach the maximum load specified (see datasheet for this info), then you should be able to reach 100MHz. Let me confirm this. 

    Best Regards, 
    Yordan

  • 0 in reply to Yordan Kovachev
    Prodigy 180 points
    Hi Yordan,

    Yes, I'm aware of that phrase from the AM335x TRM. however we would like to see the "official" TI correction on the statement:
    “Up to 100 MHz external memory clock performance (single device)”.

    we feel that the maximum capacitive load specification on the GPMC should have been enough; there is no need for the "(single device)" mentioning.... unless there is something there not clearly specified.....this possible "something" is what had us confused a bit....and requested clarification...

    regards,
    Catalin
  • 0 in reply to Catalin Palade
    TI__Guru**** 161600 points

    Catalin,

    I talked with the design team.
    The interface was timing closed for 100MHz with a the max load, but timing closure did not comprehend any signal integrity issues created when you attach four devices to a bus. The effect of stubs and impedance mismatches on the signals when attaching multiple devices will need to be considered when designing the PCB. The customer should simulate their PCB layout and make the appropriate adjustments to resolve signal integrity issues that compromise timing.

    Best Regards,
    Yordan