I have found a problem about I2S and DMA when I used them on my evaluation board(TMS320VC5505). The problem is described as follows:
Set I2S2 left channel transmit and receive in Loopback Mode. Use CSL_DMA_CHAN6 for left channel transmitting, and CSL_DMA_CHAN7 for left channel receiving.
Uint16 Tx[64] = {1,2,3,...,...,62,64}.
Uint16 Rx[64] = {x,x,x,...,...,x,x}.
Tx is CSL_DMA_CHAN6 source buffer. Rx is CSL_DMA_CHAN7 destination buffer.
When CSL_DMA_CHAN7 is set in Auto Reload Mode, Rx[64] = {62,63,64,1,2,...,...,60,61} once first DMA receive interrupt occurs. The first 61 data isn't received. It is incomprehensible.
When CSL_DMA_CHAN7 is set in Non-Auto Reload Mode, Rx[64] = {0,0,0,0,1,2,3,...,...,59,60} once first DMA receive interrupt occurs. Data are in right order according to sprz281b.pdf.
Why does DMA miss the first 61 data when CSL_DMA_CHAN7 is set in Auto Reload Mode? And why does VC5505 have the difference between Auto Reload Mode and Non Auto Reload Mode using I2S?
I need use I2S in DMA Auto Reload Mode and I do need get the right sequence in Rx buffer. This is very important to me. Would do you please provide some suggestions to me if you have meet similar problems?
Additionally, below are I2S2 and DMA configurations:
1. I2S2 configuration
I2S_Config i2sParams = {
/* Type of the data to be tx.rx */
I2S_STEREO_ENABLE,
/*Loopback mode enable/disable */
I2S_LOOPBACK_ENABLE,
/* Left Channel transmission polarity */
I2S_FSPOL_HIGH,
/* Clock polarity */
I2S_FALLING_EDGE,
/* I2S data delay */
I2S_DATADELAY_ONEBIT,
/* Data pack bit */
I2S_DATAPACK_ENABLE,
/* sign of the data to be tx/rx*/
I2S_SIGNEXT_DISABLE,
/* Number of bits in a word*/
I2S_WORDLEN_16,
/*I2S device operation mode */
I2S_MASTER,
/* Data format */
I2S_DATAFORMAT_LJUST,
/* FSDIV value */
I2S_FSDIV32,
/* Clock divisor */
I2S_CLKDIV4,
/* Frame-sync error reporting enable/disable */
I2S_FSERROR_DISABLE,
/* Overrun or under-run error reporting enable/disable */
I2S_OUERROR_DISABLE
};
2. DMA configuration
static CSL_DMA_Config dmaConfigTxm = {
#if ((defined(CHIP_5515)) || (defined(CHIP_5514)))
CSL_DMA_PING_PONG_DISABLE,
#endif
CSL_DMA_AUTORELOAD_ENABLE,
CSL_DMA_TXBURST_1WORD,
CSL_DMA_EVENT_TRIGGER,
CSL_DMA_EVT_I2S2_TX,
CSL_DMA_INTERRUPT_DISABLE,
CSL_DMA_WRITE,
CSL_DMA_TRANSFER_IO_MEMORY,
128,
0,
0x2A08
};//CSL_DMA_CHAN6
static CSL_DMA_Config dmaConfigRcv = {
#if ((defined(CHIP_5515)) || (defined(CHIP_5514)))
CSL_DMA_PING_PONG_DISABLE,
#endif
CSL_DMA_AUTORELOAD_ENABLE, //CSL_DMA_AUTORELOAD_DISABLE
CSL_DMA_TXBURST_1WORD,
CSL_DMA_EVENT_TRIGGER,
CSL_DMA_EVT_I2S2_RX,
CSL_DMA_INTERRUPT_ENABLE,
CSL_DMA_READ,
CSL_DMA_TRANSFER_IO_MEMORY,
128,
0x2A28,
0
};//CSL_DMA_CHAN7
