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DM365 : UBL and GEL Files discrepancies with the datasheet about PLL settings

reda38
Expert 1455 points

Hello TI staff,

I post today to get an answer about a strange point I saw either in GEL files or UBL.

I saw that in PLL CTL register there are bits which are used in these files and not present in the DM365 ARM Subsystem datasheet :

1-Especially the CLK_SRC which chooses the Oscillator Source to be input in the PLL.

2-In PREDIV register there is always a bit set to 1 in high weight as seen in exemple     PLL2->PREDIV =   0x8000|0x18;  where 0x18 is the ration value we want to write.

    No explanation is done about the 0x8000. Intelligent guess says it is an enable but there is a documentation problem here.

3-And there is a lack of clocks alignment in PLL ALNCTL register. It is said that clocks must be aligned. And reset values are not all set so an action is required.

Can somebody tells me if the UBL code is up to date with the DM365 ? It looks like it is only a porting of DM355 code.

Thank you for your answers.

  • 0
    TI__Expert 5955 points

    Regarding 2- you are correct about bit15 of this register. It is for disable/enable the pre-divider of the PLL1/PLL2. We will update the ARM SS doc to address the missing info.

    All UBLs have the same framework. So they look similar. Which version of UBL are you using?

    Thanks,
    Tai

  • 0 in reply to Tai Nguyen
    Expert 1455 points

    Hello Taï,

    Thank you for answering. But for point 2- is some information missing or is it extra not needed information ?

    For issue 1, is it still a documentation problem ? what would be the right thing to write ?

    For point 3- it is also stunning, that required operation are not done in UBL. But maybe it was found unuseful and that the hardware is roust enough or i miss something about clock alignment in the specifications. To summarize it is hard to choose between the datasheet which indicates things to do, and the UBL code which implements things which work. Hard decision making.

    The UBL version i use is 1.50. But I modified it because my hardware required some changes in pinmux, aemif, peripheral clocks, etc... it is a good point that we can modify it.

    Cheers

     

     

  • 0 in reply to reda38
    TI__Expert 5955 points

    Hello,

    For issue 1, the PLL_CTL bit 8 is a don't care and that is why it is documented as reserved. The internal oscillator mode is enabled all the time for PLL1.

    For issue 2, similarly, bit 15 of the PRE_DIV register, the PRE_DIV enable/disable bit is tied off to enable so it is a don't care and documented as reserve but it is recommended to write as a "1" to be safe as the GEL does.

    For issue 3, it is recommended to follow the data sheet as you modify the UBL.

    Thanks.

    -Tai Nguyen 

  • 0 in reply to Tai Nguyen
    Expert 1455 points

    Hello Taï Thank you for your answer

    For issue 2 and 3, it is OK. I have done as you say.

    Concerning point 1, you say that :"The internal oscillator mode is enabled all the time for PLL1". Does that mean that the external clock oscillator of 24MHz is of no use for PLL1 ?



  • 0 in reply to reda38
    TI__Expert 5955 points

    Hello,

    It means that with this configuration the PLL will work with either crystal or oscialltor clock. The drawback is the internal oscillator is enabled all the time until it goes into the deep sleep mode.

    Thanks.

    -Tai Nguyen