Hi all,
I had a custom board using C6657.
We found 650mV leakage from +V1.0_S0_DSP (CVDD1) to +V1.5_S0_DDR3 (DVDD15) supplies during power-up sequencing. Then also make sure a maximum of 100ms between one power rail being valid, and the next power rail in the sequence starting to ramp. Does this negatively impact device operation or reliability?
Thanks in advance.
B.R.
OC