Team, please prioritize the question below from my customer:
We downloaded the dra7xx RTOS package which seems to include the PDK for de Jacinto.
Now we are trying to understand what is the required configuration between M4 and A15 in terms of memory mapping and peripheral sharing.
The example provided here http://processors.wiki.ti.com/index.php/Early_Boot_and_Late_Attach didn't work. It generates a panic after loading and attempting to run the IPU1.
What would be a good document to understand the correct M4/A15 setup?
