Part Number: TMS320C6670
Hi all,
My question is not an issue, but just deals with requesting help in understanding the IPC transport over QMSS.
I am implementing an IPC transport over QMSS functionality for my project on the C6670, and I have been reading through the IPC section of the BIOS-MCSDK 2.0 User Guide.
Reference the ladder diagram titled "IPC QMSS Transport Message Passing" in the MCSDK user guide. When one core sends a MessageQ message to another core via QMSS, the sending core pops a free descriptor off the Free Queue, adds a pointer to the message to the descriptor, writebacks the message and descriptor to shared memory, and pushes the descriptor onto the remote processor's Receive Queue.
In my particular case, I want to use monolithic descriptors so the descriptor contains the packet data (which is the MessageQ message) and not just a pointer to the data like in a host descriptor.
I am wondering why would I wrtiteback the message and the descriptor to shared memory when I am using the QMSS to transport the message, which is contained within the packet data of a monolithic descriptor?
Thanks.
Rawley
