This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UPP pin muxing

I know I saw an explanation for this either on the forum's or the wiki, but now I can't seem to locate it...

In the OMAP/c6748 pin muxing program, the UPP control pins for Channel A are labeled as UPP_CH1... and the Channel B control pins appear to be labeled as UPP_CH0..., which leads to some confusion as to which pin group is which.

Also according to the UPP guide, the Data and XData pins used are not static and depend on the UPCTL configuration further complicating matters.

I want to use the UPP channel B in receive mode interfaced to a 16-bit ADC.   If I set the UPCTL bits CHN, IWA, and IWB according to Table 3 in the User's Guide with CHN =1, IWA = 0, and IWB = 1, then I would interface the ADC with:

ADC[15:8] = XDATA[15:8]

ADC[7:0] = DATA[15:8]

CLK = UPP_CH0_CLK (pin G1)

START = UPP_CH0_START (pin G2)

ENABLE = UPP_CH0_ENABLE (pin J4)

WAIT = UPP_CH0_WAIT (pin G3)

Is that correct?

 

  • The settings look correct, however as shown in Table 4 of the user guide, channel B can only be used in 2-channel mode. If you plan to operate only in 1-channel mode you have to use channel A.

     

    Jeff

  • Jeff,

    I'm not sure what running in 2-channel mode rather than 1-channel mode implies in this case. In 2-channel Receive mode, can't I just control and receive 16-bit data on the B channel, and ignore the A channel control and data pins or multiplex them for some other use?

    Ryan

  • Even if the A channel pins are multiplexed for another use, the uPP peripheral will still see them as inputs which could cause problems. If you dont use them for anything else, you will want to tie certain pins off, like WAIT, to inactive values.

    Is there a reason you don't want to use channel A, as is intended for single channel operation? Then channel B pins could be used for another purpose without any issues.

    Jeff

  • Jeff,

    I'm just exploring different configuration possibilities. For our application we want to use the UPP, the PRU and EMIFA -- in that order of importance. Maximizing the functionality of the UPP (and using the A channel) and PRU leaves only a few EMIFA address pins to work with . Attached to the EMIFA will be just a few registers inside an FPGA, so the 7 or so remaining address pins should be enough. It would just be nice to have a little more memory space available to the EMIFA in case we need to hang something else on there in the future.

     

    Thanks

     

    Ryan

  • Understood. If the channel A control signals are tied to the right values and not used as PRU pins, then there shouldn't be an issue with using only channel B.

    Jeff

  • That's the problem. The channel A control signals would be some of the one's we need for the PRU in that particular configuration. I think based on what you've said, the safest thing to do would be to use Channel A and then just have a limited address range on the EMIFA. Do you agree?

    Ryan 

  • Ok in that case use should use Channel A as you stated.

    Jeff

  • Jeff,

    Thanks. I appreciate your help. It seems that although the pin mux will allow you to create certain configurations, some of those may not necessarily work the way you would expect them too. Would you mind looking at my pin selections/mux file and make sure I don't have anymore potential "gotchas" in there?

    Ryan

  • Sure, you can attach it here if you would like.

    Jeff

  • Here's the .pin file. I had to change the extension to .txt so it would take it. I have copy and pasted the header file below.

    Thanks

    Ryan

    /*

    MUX1 Pins:

    SPI0_CLK SPI0_ENA SPI0_SOMI SPI0_SIMO SPI0_SCS[5] SPI0_SCS[4] SPI0_SCS[3] SPI0_SCS[2] SPI0_SCS[1] SPI0_SCS[0]

    EMA_BA[1] EMA_BA[0] EMA_CS[0] EMA_CS[2] EMA_CS[3] EMA_CS[4] EMA_CS[5] EMA_WE EMA_OE EMA_RNW

    EMA_WAIT[0] EMA_D[15] EMA_D[14] EMA_D[13] EMA_D[12] EMA_D[11] EMA_D[10] EMA_D[9] EMA_D[8] EMA_D[7]

    EMA_D[6] EMA_D[5] EMA_D[4] EMA_D[3] EMA_D[2] EMA_D[1] EMA_D[0] EMA_A[6] EMA_A[5] EMA_A[4]

    EMA_A[3] EMA_A[2] EMA_A[1] EMA_A[0]

    MUX2 Pins:

    ECAP0_APWM0 UART1_RXD UART1_TXD PRU1_R30[8]

    MUX3 Pins:

    UART1_RTS UART1_CTS ECAP2_APWM2 ECAP1_APWM1 TM64P2_OUT12 TM64P3_OUT12 I2C1_SCL I2C1_SDA PRU1_R30[31] PRU1_R30[30]

    PRU1_R30[29] PRU1_R30[28] PRU1_R30[27] PRU1_R30[26] PRU1_R30[25] PRU1_R30[24] PRU1_R30[23] PRU1_R30[22] PRU1_R30[21] PRU1_R30[20]

    PRU1_R30[19] PRU1_R30[18] PRU1_R30[17] PRU1_R30[16] PRU1_R30[15] PRU1_R30[14] PRU1_R30[13] PRU1_R30[12] PRU1_R30[11] UPP_CH1_CLK

    UPP_CH1_START UPP_CH1_ENABLE UPP_CH1_WAIT PRU1_R30[10] PRU1_R30[9] UPP_D15 UPP_D14 UPP_D13 UPP_D12 UPP_D11

    UPP_D10 UPP_D9 UPP_D8 UPP_D7 UPP_D6 UPP_D5 UPP_D4 UPP_D3 UPP_D2 UPP_D1

    UPP_D0 PRU1_R30[7] PRU1_R30[6] PRU1_R30[5] PRU1_R30[4] PRU1_R30[3] PRU1_R30[2] PRU1_R30[1] PRU1_R30[0]

    MUX4 Pins:

    GP7[15] GP7[14] GP7[13] GP7[12] GP7[11] GP7[10] GP7[9] GP7[8] GP7[7] GP7[6]

    GP7[5] GP7[4] GP7[3] GP7[2] GP7[1] GP7[0]

    MUX5 Pins:

    TM64P2_IN12 TM64P3_IN12

    */

    #define PINMUX0_VALUE 0x00440000

    #define PINMUX1_VALUE 0x40000004

    #define PINMUX2_VALUE 0x20000000

    #define PINMUX3_VALUE 0x11111111

    #define PINMUX4_VALUE 0x22444411

    #define PINMUX5_VALUE 0x11000000

    #define PINMUX6_VALUE 0x10000000

    #define PINMUX7_VALUE 0x11111111

    #define PINMUX8_VALUE 0x11111111

    #define PINMUX9_VALUE 0x11111111

    #define PINMUX10_VALUE 0x44444444

    #define PINMUX11_VALUE 0x44444444

    #define PINMUX12_VALUE 0x11111114

    #define PINMUX13_VALUE 0x44444444

    #define PINMUX14_VALUE 0x44444444

    #define PINMUX15_VALUE 0x44444444

    #define PINMUX16_VALUE 0x88888844

    #define PINMUX17_VALUE 0x88888888

    #define PINMUX18_VALUE 0x44200088

    #define PINMUX19_VALUE 0x00444444

     

  • Jeff,

    Did you ever have a chance to look at my mux settings?

    Ryan

  • Sorry for the delay. I took a look and didnt find any issue with your muxing.

    Jeff