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RTOS/TMS320C6678: Configure MSM to be non-cacheable in L1D when L2 is configured as SRAM?

David Hague
Intellectual 560 points
Part Number: TMS320C6678

Tool/software: TI-RTOS

We have a main program running on Core 0 and “helper” programs running on Cores 1-5.  The Core 1-5 programs are identical.   The main program on Core 0 puts into MSM data for the Core 1-5 programs to munch on and they return the results also in MSM.  Each Core has its own location in MSM so there’s no need for them to “coordinate” with each other.  We are using the Semaphore2 mechanism for synchronicity between Core 0 and the Helpers.

 

Also, its’ worth noting that we don’t have any DDR memory.  All of the programs run out of their respective L2 memory.  Thus, ALL L2 memory is configured as SRAM, none of it is configured as cache.

 

What I think I’ve discovered is that when L2 is configured as SRAM, the MSM is automatically configured to be cached by L1D.   This presents a problem in that if Core 0 writes data to MSM, Cores 1-5 will not see this new data if the previously read data is in their L1D.  And the same happens if Cores 1-5 write data and Core 0 wants to read it.

 

The same thing happens when DMA is used.  And we’re doing a LOT of DMA.

 

The solution, of course, is to “invalidate L1D” before reading a location in MSM.  But this is going to be a pain because Core 0 and Cores 1-5 do a LOT of reading from MSM in many, many places throughout the code.  It is just going to be a LOT of invalidating.

 

We can also completely invalidate ALL of L1D caching, but L1D exists to speed up processing and we also have very tight timing requirements so we would like to take advantage of L1D where we can.

 

The perfect solution would be to configure MSM as “non-cacheable”.  I can do this in VxWorks and every other RTOS that I’ve ever used.   But from reading other posts in the Forum and scouring the TI Documentation, this does not seem to be possible with TI-RTOS.  I’ve even seen responses from TI in the Forum where they say it is not possible to turn off caching for selective memory regions.  Only invalidating, which must be done every time you want to read it.

 

So, to boil it all down to one question:   Is it possible to configure MSM to be non-cacheable for L1D when L2 is used as SRAM?

 

Thanks,

David Hague

  • 0
    TI__Guru 65405 points
    Hi David,

    I've forwarded your query to the software experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • 0 in reply to Cvetolin Shulev-XID
    Intellectual 560 points

    We are using pdk_c667x_2_0_0.   I’ve also found a couple of different ways to possibly do this.  One, using CSL_XMC_setXMPAXH() calls and another just setting the register directly.  But it is not working for me.  I’m sure I’m doing something wrong, I just don’t know what.  As I understand it, MSMC is at address 0x0C000000 but I can’t set the MAR bit for that address to turn off caching.  So, I create an alias for that address at 0xA0000000 and then I set the MAR bit for that address.   So when I set up my DMA, I make the destination address 0xA00000000, right?  Here’s the code I have:

     

       /*

       **  Using MPAX register 3

       **  Segment size : 4 MB (0x15 = 0b10101)

       **  Logical address : 0xA000_0000 (0x00A00)

       **  Physical address : 0x0C00_0000 (MSMC) (0x000C0)

       **  Protection for supervisor and user : read, write, no execution (110110)

       **  MAR Register index for 0xA000_0000 : 160 (0xA0)

       */

       CSL_XMC_XMPAXH highStruct = {0xA0000, 0x15};

       CSL_XMC_XMPAXL lowStruct  = {0x00C000, 1, 1, 0, 1, 1, 0};

     

       CSL_XMC_setXMPAXH (3, &highStruct);

       CSL_XMC_setXMPAXL (3, &lowStruct);

     

       CACHE_disableCaching (160);

     

     

    I also just tried doing:

     

       *((uint32_t *)0x0800001C) = 0xA0000015;

       *((uint32_t *)0x08000018) = 0x00C00036;

       *((uint32_t *)0x01848280) = 0x00000000;

     

     

    Which does the same thing.  I can look at these addresses in the memory browser and see that they are getting set.

     

    I then changed my code to have the destination address be 0xA0000000 instead of 0x0C000000.  Except nothing happens.

     

    Are there multiple MPAX's to configure for the CorePac and EDMA3 to access alternate addresses for the MSM SRAM?

     

    Thanks

    David

     

  • 0 in reply to David Hague
    Intellectual 560 points

    The EDMA3 exists outside of any core and requires "global" addresses.  It doesn't know anything about Aliasing either.  So, the Core 0 code will uses the 0xA0000000 address, but when setting up the EDMA3, the 0x0C000000 address needs to be used.  This seems to have solved our problem

  • 0 in reply to David Hague
    TI__Mastermind 23125 points

    David,

    It seems that you were able to disable MSMC caching now. As to the core-to-core coherency, the MSMC on this device does not support it. So you have to manually manage the data exchange.

    Please let us know if there additional issues.

    regards

    jian