Hello again, I am trying to draw up a simple cartoon explain the boot process. What I have need is to make sure how I understand the datasheets correctly. In my own words:
AFTER POWER SEQUENCE HAS COMPLETED:
(BOOTMODE[15:0] pins map to DEVSTAT[16:1] bits)
ARM COREPAC0 IS BOOT MASTER AND SPI PORT 1 IS BOOT PORT
SPI SERIAL PORT DATA AND STORES TO MSMC
WHICH INITIALIZES THE DDR3L EXTERNAL MEMORY
THE MSMC BOOT CODE INTO EXTERNAL DDR3L
READ ALL CORE’S APPLICATION PROGRAM/DATA
FROM SPI FLASH AND STORE INTO SPECIFIED GP HEADER
ADDRESS MEMORY SPACE (LOCAL OR GLOBAL)
DSPCOREPAC 0-3 AS NEEDED USING THE IPC REGISTERS
MEMORY LOCATION INDICATED BY THE MASTER CORE
Is this correct? I am a little bit confused about where the cores will run from, but know the master boot ARM must make sure the code is properly placed. The question also arose as to what happens if the program for a particular core is too big for their local memory where we want each to run from. I do not think the system was intended to run all the cores out of DDR3L, but please enlighten me so that I can finish a cartoon block diagram and describe it clearly to all of our team members who will be involved in coding the radar system. thanks -b
