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AM1808 DDR2 routing constraints

Jeff Oberski
Prodigy 140 points
Other Parts Discussed in Thread: AM1808

Just how critical is it to meet DQLM and CACLM, the DQS/D and CAC nominal trace length parameters? My current routing exceeds DQLM by 650-700 mils. Fixing this will require rotating the DDR memory 90 degrees counter-clockwise which will require moving a bunch of other stuff. I'm also a bit out on CACLM. However I don’t understand why matching net classes to their max Manhattan length would matter all that much. It should be enough to match net classes within themselves and to their clocks, and keep the max lengths reasonable in comparison to the clock cycle time.

Routing length analysis below:

Pre-Term   Post-Term pre length post length Total Length CACLM Max Delta to CACLM Actual Delta to CACLM Max CAC to CAC Skew Actual CAC to CAC Max Skew Actual CAC to CAC Min Skew Max CLKP to CLKN Skew Actual CLK Skew
P_DDR_CLKN M_DDR_CKP 249.93 970.36 1220 1177 50 43 100 -53 14 25 14
P_DDR_CLKP M_DDR_CKN 232.47 974.11 1207 1177 50 30 100 -66 0 25 -14
P_DDR_A0 M_DDR_A0 257.33 997.09 1254 1177 50 77 100 -19 48
P_DDR_A1 M_DDR_A1 233.76 974.1 1208 1177 50 31 100 -65 1
P_DDR_A10 M_DDR_A10 245.59 979.1 1225 1177 50 48 100 -48 18
P_DDR_A11 M_DDR_A11 259.18 975.37 1235 1177 50 58 100 -39 28
P_DDR_A12 M_DDR_A12 246.04 981.3 1227 1177 50 50 100 -46 21
P_DDR_A13 M_DDR_A13 236.16 998.68 1235 1177 50 58 100 -38 28
P_DDR_A2 M_DDR_A2 246.58 988.31 1235 1177 50 58 100 -38 28
P_DDR_A3 M_DDR_A3 233.05 975.45 1209 1177 50 32 100 -65 2
P_DDR_A4 M_DDR_A4 238.35 986.18 1225 1177 50 48 100 -49 18
P_DDR_A5 M_DDR_A5 238.5 991.65 1230 1177 50 53 100 -43 24
P_DDR_A6 M_DDR_A6 240.86 987.26 1228 1177 50 51 100 -45 22
P_DDR_A7 M_DDR_A7 233.1 978.71 1212 1177 50 35 100 -61 5
P_DDR_A8 M_DDR_A8 272.77 1000.28 1273 1177 50 96 100 0 66
P_DDR_A9 M_DDR_A9 240.02 986.51 1227 1177 50 50 100 -47 20
P_DDR_BA0 M_DDR_BA0 232.94 998.2 1231 1177 50 54 100 -42 25
P_DDR_BA1 M_DDR_BA1 278.39 991.38 1270 1177 50 93 100 -3 63
P_DDR_BA2 M_DDR_BA2 243.95 985.75 1230 1177 50 53 100 -43 23
P_DDR_CASN M_DDR_CASN 268.14 989.13 1257 1177 50 80 100 -16 51
P_DDR_CKE M_DDR_CKE 233.59 979.26 1213 1177 50 36 100 -60 6
P_DDR_CSN M_DDR_CSN 267.28 1000.24 1268 1177 50 91 100 -6 61
P_DDR_RASN M_DDR_RASN 266.79 986.76 1254 1177 50 77 100 -20 47
P_DDR_WEN M_DDR_WEN 235.97 989.27 1225 1177 50 48 100 -48 19
Average 1233
Pre-Term   Post-Term Pre-Term Length Post-Term Length Total Length DQLM Max Delta to DQLM Actual Delta to DQLM Max D to DQS Skew Actual D to DQS Skew Max D to D Skew Actual D to D Max Skew Actual D to D Min Skew Max DQS to DQS Skew Actual DQS to DQS Skew
M_DDR_D0 P_DDR_D0 255.91 1686.63 1943 1271 50 672 100 -1 100 0 27  
M_DDR_D1 P_DDR_D1 251.83 1665.6 1917 1271 50 646 100 -26 100 -25 1  
M_DDR_D2 P_DDR_D2 264.3 1659.1 1923 1271 50 652 100 -20 100 -19 7  
M_DDR_D3 P_DDR_D3 258.07 1666.33 1924 1271 50 653 100 -19 100 -18 8  
M_DDR_D4 P_DDR_D4 259.87 1666 1926 1271 50 655 100 -18 100 -17 10  
M_DDR_D5 P_DDR_D5 250.5 1665.54 1916 1271 50 645 100 -28 100 -27 0  
M_DDR_D6 P_DDR_D6 266.06 1658.61 1925 1271 50 654 100 -19 100 -18 9  
M_DDR_D7 P_DDR_D7 252.55 1664.58 1917 1271 50 646 100 -27 100 -25 1  
M_DDR_DQM0 P_DDR_DQM0 264.26 1665.13 1929 1271 50 658 100 -14 100 -13 13  
M_DDR_DQS0 P_DDR_DQS0 263.49 1680.24 1944 1271 50 673           25 2
M_DDR_D8 P_DDR_D8 287.68 1672.47 1960 1271 50 689 100 18 100 -14 50  
M_DDR_D9 P_DDR_D9 251.32 1663.78 1915 1271 50 644 100 -27 100 -59 5  
M_DDR_D10 P_DDR_D10 252.02 1674.66 1927 1271 50 656 100 -15 100 -47 16  
M_DDR_D11 P_DDR_D11 286.44 1687.6 1974 1271 50 703 100 32 100 0 64  
M_DDR_D12 P_DDR_D12 278.69 1662.47 1941 1271 50 670 100 -1 100 -33 31  
M_DDR_D13 P_DDR_D13 258.67 1679.63 1938 1271 50 667 100 -4 100 -36 28  
M_DDR_D14 P_DDR_D14 252.13 1658.18 1910 1271 50 639 100 -32 100 -64 0  
M_DDR_D15 P_DDR_D15 250.75 1663.2 1914 1271 50 643 100 -28 100 -60 4  
M_DDR_DQM1 P_DDR_DQM1 291.3 1658.96 1950 1271 50 679 100 8 100 -24 40  
M_DDR_DQS1 P_DDR_DQS1 280.55 1661.39 1942 1271 50 671           25 -2
Average 1932
Pre-Term1   Pre-Term2 Post-Term Pre-Term1 Length Pre-Term2 Length Post-Term Length Total Length CKB0B1 Max Skew to CKB0B1 Actual Skew to CKB0B1
P_DDR_DQGATE0 P_DDR_DQGATE1 DDR_DQGATE 1039.14 1041.67 1036.8 3118 3156 100 -39
  • 0
    TI__Mastermind 27585 points

    The purpose of CACLM and DQLM is to constrain the total length of the traces. Even though they may be skew matched and the memory is placed near the controller, it is possible to make the traces where the length exceeds our simulations.

    In your case since your DDR is not placed at the maximum allowed distance, you can exceed CALCM and DQLM as well. A part placed at the maximum distance will have a CACLM/DQLM of around 2400 mils, so if you are below that you are ok.

    A question this brings up is why are the data lines so long in comparison to the address lines? In a single memory system everything should be point to point and relatively direct, right?

    Jeff

  • 0 in reply to jc-ti
    Prodigy 140 points

    Thanks for your answer.

    In regards to your question about the data line lengths, I am concerned about SI and EMI, so my design includes series terminators. Half of the DQ/DQS terminators had to be located on the side of the memory opposite from the processor. This caused longer routing lengths. Additionally, I rotated the memory 90 degrees clockwise from the way it is shown in the AM1808 datasheet and placed it roughly on center with the processor. This was done to relieve routing congestion, but had the side effect of further shortening the addr lines in relation to the DQ/DQS lines.

    --Jeff

  • 0
    Intellectual 995 points

    It may help you also to look at the pcb layout of the Hawk board(uses L138); they have rotated the Ram chip 90 degrees. and as a result some of the lines look longer. the Schem, Pcb are open source: www.hawkboard.org

    Hope it help you.