AM3351: DDR failures on the board

Hi Mitchell
RJ escalated this thread, and we will be looking at this.
The key power management expert is on travel this week.

for completeness i am also linking the discussion you or your customer have had on this topic on the PMIC forums

e2e.ti.com/.../2202633

Were you planning to attach the timing diagrams to this post?

Regards
Mukul

Hi Mukul,

I’ve requested the timing diagrams from the customer. Once I get something back I’ll post them to this thread.

Thanks,
Mitchell

Hi Mukul,

Here is the timing diagram:

Thanks,
Mitchell

Hi Siva,

Thanks for the very quick feedback! For the mis-sequencing of the VDDS rail, what are the effects of this? Could this be harming some other part of the system?

Unfortunately, we do not have a voltage waveform at the VDDS_DDR node when this problem is present.

Thanks,
Mitchell

We have a couple follow-up questions regarding the feedback given above. I know some have already been addressed and closed, but wanted to post here for reference. There is still some confusion around questions #2, as I’ve come across a couple instances that suggest it’s okay to connect VDDS separately on LDO3. I'd really like to get some clarification on this.

1) If we are powering the VDDS domain also from the VRTC, then in the RTC only mode, LDO1 will still be powering the VDDS; will it not? If that’s the case, how can we achieve the minimum current consumption?

SIVA>> In this configuration, unfortunately, RTC only mode cannot be supported.

2) In the Beagle Bone reference design, there is an option to power VDDS separately from LDO3. How is it going to work in that mode?

SIVA>> I’m not sure if I follow you – are you indicating that LDO1 is powering only VDDS_RTC? This would be a violation of the sequence as we discussed earlier. Let me check and confirm if there is any issue with Beaglebone.

3) Could you please make it a little more clear how this can create an unstable operation from the PMIC side? I am not clear how a PMIC output can go unstable due to a mismatch in the sequence and if so which is the feedback path for the DCDC controller to detect the sequencing issue.

SIVA>> I’m not entirely sure if the PMIC stability issue is related to the sequence violation. However, it would be good to verify with the right sequence

Thanks,
Mitchell

Regarding Q2, I checked the Beagle bone schematic. I don't see any issue since LDO1 is being used to power the VDDS and VDDS_RTC. This will ensure that they are the first to be ramped up and is aligned with the data sheet requirements. I do understand there is a provision for powering VDDS from LDO3, but is DNI and is not the right option for meeting the power sequencing requirements of the processor.

Let me know if you have any further questions

Hi Siva,

Thank you for the clarification. In this particular use-case, power consumption is a huge concern and they want to be able to go into RTC only mode to maximize battery life. If they fix the sequencing as suggested, they will no longer be in this ‘mode’.

Are there any tricks that we can do to enable RTC only mode while also maintaining the proper sequencing?

Thanks,
Mitchell

Hi Siva,

I don’t think switching to the TPS65218 will work since it does not have an integrated charger.

If they tie VDDS to LDO1 on the current device, I understand RTC-only will not work.

But, with the help of many other threads on this topic, I've seen a couple 'hardware tricks' which allow this mode of operation. One idea that's come up a few times is to connect a separate regulator for the 1V8 VDDS component and activate it with the PWR_EN signal.

To manage shutdown sequence, control the 1V8 regulator with PWR_EN or’d with VDD_DDR. This would turn it on when PWR_EN is applied, and then turn it off only after the DDR voltage has dropped (making it the last thing to turn off). Will this work to achieve the required sequence + RTC-only mode?

And if so, do we have a schematic to showcase this configuration?

Thanks,
Mitchell

Mitchell said:

 
I don’t think switching to the TPS65218 will work since it does not have an integrated charger.

If they tie VDDS to LDO1 on the current device, I understand RTC-only will not work.

Yes. That is correct. If they tie VDDS to LDO1, then RTC-only will not work

Mitchell said:

But, with the help of many other threads on this topic, I've seen a couple 'hardware tricks' which allow this mode of operation. One idea that's come up a few times is to connect a separate regulator for the 1V8 VDDS component and activate it with the PWR_EN signal.

I'm not sure how this will work overall. How do you expect the 1.8V VDDS to power-up before all the other rails in case of using the PWR_EN as the Enable for the external regulator. If you could provide a block-diagram of what you are thinking, I can review and provide feedback

Mitchell said:

To manage shutdown sequence, control the 1V8 regulator with PWR_EN or’d with VDD_DDR. This would turn it on when PWR_EN is applied, and then turn it off only after the DDR voltage has dropped (making it the last thing to turn off). Will this work to achieve the required sequence + RTC-only mode?

And if so, do we have a schematic to showcase this configuration?

We don't have any schematic to show the external regulator option for VDDS. One key thing to consider is the supply for the OR gate and make sure you are able to comprehend both power-up and down sequence that meets the data sheet requirements.

Regards, Siva

Hi Siva,

Basically, I'm referring to this E2E post. I've put together a rough block diagram, seen below.

Let me know if this implementation would work.

Thanks,
Mitchell

Mitchell,

Looking through your block diagram, I'm not sure if you really want to use a Load Switch on LDO1 since there would be Iq on the load switch during RTC-only mode. Did you evaluate if this additional Iq would be fine during RTC only mode?

I think you have a typo on the DCDC3. DCDC3 should be mapped to VDD_CORE and DCDC2 should be mapped to VDD_MPU. LS1/LDO3 should be used for 1.8V Analog rails. Please use the app note : www.ti.com/lit/ug/slvu551i/slvu551i.pdf for verifying the processor and PMIC connections.

Also, couple of other things to consider here:

- Entry/Exit into and out of RTC-only (sleep) mode to active mode. PWR_EN is used for transitioning between sleep and active modes. With the scheme you proposed, I'm confused since you show PWR_EN is driven from the PMIC, but it is actually an input to the PMIC from the SoC

- You can use the PWR_EN of the SoC, but this will not work for power-down if you directly use it with the scheme you listed here specifically entering RTC-only mode

- Looking at all your requirements, I would recommend either of the following to make the design compatible with all the power management and sequencing requirements

Option 1:Use external LDO to power VDDS and VDDSHVx and use the PWR_EN. Basically, you have to make sure that power-down sequence is also satisfied. To accomplish this, you would need to add a diode between PWR_EN to the EN of the external LDO. The EN of the external LDO should be pulled up to VDDS_DDR and also add a capacitor to make sure VDDS and VDDSHVx is the last rail to ramp-down.

Option 2: Use an external RTC and the TPS65217 LDO1 to power VDDS, VDDSHVx of SoC

Let me know if you still have any other questions.

Regards, Siva

Hi Siva,

Just want to verify, I don't think there is a typo in the block diagram on DCDC2. Since we are using the ZCE package of the AM3351, VDD_MPU is internally connected to VDD_CORE. This should make the connection at DCDC2 acceptable.

With that in mind, I see that there is a potential mismatch in some of the 1.8V lines which might need to be moved over to LDO3 (i.e. VDDSHVx(1.8V), VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU_BB, VDDA1P8V_USB0, and VDDA_ADC); however, if this converter is freed up now, is it okay to leave these connected to DCDC3?

I can send you the schematic if that will make this a little easier.

Also, thank you very much for the 2 options you suggested. We will take these into consideration.

Thanks,
Mitchell