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C5505 USB Peripheral - how do the interrupts work?

TommyG
Genius 13045 points

It's not clear from the USB PRG how the interrupts work in the USB peripheral.  There appear to be 2 different sets of registers that control interrupts.  There are the USB Interrupt Source / Mask regeisters described in Table 13 and sec 3.10 - 3.16.  Then there are registers in the USB2.0 Core described in Table 14 and sec 3.25 - 3.29.  How are these registers related and how do they need to be used?  Do they all need to be used?  Can someone explain the details?  It would be nice if there were some block diagram or flow chart to clarify this.  I've looked at the CSL Interrupt example, but it is not clear to me.

Thanks.

 

  • 0
    Expert 2605 points

    Hi Tommy, 

    C5505/15 USB core provides interrupt handling mechanism at two levels. One is the core level which will be provided by the Mentor core. To handle the interrupts at core level you have to use the interrupt register set described in sec 3.25 - 3.30 (INTRTX, INTRRX, INTRTXE, INTRRXE, INTRUSB and INTRUSBE). On the top of this core level there is wrapper logic which provides PDR(Peripheral Development Requirement) standard interrupts. To use the PDR interrupts you have to configure both sets of registers described in sec 3.25 - 3.30 and sec3.10 to 3.16. Using the core interrupts or PDR interrupts can be selected by configuring the bit 'UINT' of CTRLR register.

    C55xx CSL configures UINT bit to '0' hence uses PDR interrupts.

    For using the PDR interrupts

     1. Enable the core interrupts by configuring INTRTXE, INTRRXE and INTRUSB_INTRUSBE registers
     2. Enable PDR interrupts by configuring INTMSKSETR1 and INTMSKSETR2 registers
     3. Determine the source of the interrupt by reading INTMASKEDR1 and INTMASKEDR2 registers in USB isr
     4. Clear the interrupts by setting INTCLRR1 and INTCLRR2 registers

    Pratap.