• State TI Thinks Resolved
  • Locked Locked
  • Replies 9 replies
  • Answers 3 answers
  • Subscribers 99 subscribers
  • Views 2234 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320C6678: I2C boot not working

Sivanantham S
Intellectual 840 points

Part Number: TMS320C6678

Hi,

We would like to boot processor in I2C mode in our custom board. Processor is not booting.
So we are seeking your help on this. We are doing the following steps formed based on the wiki page.
 
Boot application (DSPC8682_eeprom_1.out  not included in the attachment) conversion is done as per the post_romparse.bat which is  
attached. Also post_8682_1.rmd,reboot_1.i2cmap files are linked in the conversion process.
 
Output of the above process (eeprom_1_post_8682.bin) is given to eeprom writer program
(C:\ti\mcsdk_2_01_02_06\tools\writer\eeprom\tisbc6678l\).
Note: Writer program is loaded when Processor is under No I2_boot_files.zipboot mode
 
The program log is given below
 
[C66xx_0] EEPROM Writer Utility Version 01.00.00.05
 
Writing 4168 bytes from DSP memory address 0x0c000000 to EEPROM bus address 0x0050 starting from device address 0x0000 ...
Reading 4168 bytes from EEPROM bus address 0x0050 to DSP memory address 0x0c010000 starting from device address 0x0000 ...
Verifying data read ...
EEPROM programming completed successfully.
 
Then boot mode changed to I2C bootmode (Master)
Boot_pararm(15 downto 0)<=x"000B";
0xB->1011
1-> Little  Endian
101 (5) -> I2C boot mode
0 -> Parameter Index
0 -> Master mode
0 -> Boot from I2C EEPROM at I2C bus address 0x50
0 -> I2C slow mode (both 0 -> slow and 1 ->fast mode tried)
 
00-> PCIe endpoint
0-> PCIe Subsystem enabled.
 
Is there any steps are missing? Please suggest on.

Regards,

S.Sivanantham

  • 0
    Intellectual 840 points
    Hi,
    I2_boot_files.zip file is attached in between (Note: Writer program is loaded when Processor is under No I2_boot_files.zipboot mode ) statement. Sorry for the inconvenience.

    Our board eeprom address is 0x50 and its size is 32KB from atmel.

    Regards,
    S.Sivanantham
  • 0 in reply to Sivanantham S
    TI__Guru**** 161600 points
    we're looking into this. Feedback will be posted here.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Intellectual 840 points

    Hi,

    Anybody is looking into this issue?

    We are waiting for your response.

    Regards,

    S.Sivanantham

  • 0 in reply to Sivanantham S
    TI__Guru** 116830 points
    Sivanantham,

    Have you tried to put a scope on the I2C EEPROM pins to see if the ROM code is able to read from the EEPROM? When the ROM bootloader fails have you connected to the DSP and observed where the Program counter is at? You can run the Debug GEL file that we provide here and report the device state.

    processors.wiki.ti.com/.../Keystone_Device_Architecture

    In addition to your boot parameter table, can you indicate what your DESTAT register setting is. Please provide full value of location 0x026200020.

    Regards,

    Rahul
  • 0 in reply to Rahul Prabhu
    Intellectual 840 points

    Hi Rahul,

    Thanks for reply. Please find the device status register log using c6678 debug  gel

    *******************************************************************************************************
    C66xx_0: GEL Output:  ********************************** C6678 BOOTSTRAP CONFIGURATION ******************************************************
    C66xx_0: GEL Output:  *******************************************************************************************************
     
    C66xx_0: GEL Output:  ********************************** C6678 Device Status Register (DEVSTAT) ************************************
     
    C66xx_0: GEL Output:  BOOTCFG_DEVSTAT ---> 0x0001000B  
     
    C66xx_0: GEL Output:  LENDIAN[0] ---> Little Endian
    C66xx_0: GEL Output:  BOOTMODE[3:1] ---> I2C Boot Mode
    C66xx_0: GEL Output:  SmartReflex ID[5:4] ---> 0
    C66xx_0: GEL Output:  MODE[10] ---> Master Mode
    C66xx_0: GEL Output:  ADDRESS[11] ---> Boot From I2C EEPROM at I2C bus address 0x50
    C66xx_0: GEL Output:  SPEED[12] ---> I2C data rate set to approximately 20 kHz
    C66xx_0: GEL Output:  PARAMETER IDX[9:4] ---> 0
    C66xx_0: GEL Output:  PCIESSEN[16] ---> Initial state of the power domain and the clock domain for PCIE subsystem is Enabled
    C66xx_0: GEL Output:  PCIESSMODE[15:14] ---> PCIE in End-point mode
    C66xx_0: GEL Output:  PASSCLKSEL[17] ---> SYSCLK / ALTCORECLK (controlled by CORECLKSEL pin) is used as the input to PA_SS PLL
    C66xx_0: GEL Output:  SYSCLKOUTEN[0] ---> No Clock Output
     
    C66xx_0: GEL Output:  ********************************** C6678 DIEID Register (DIEID) ************************************
     
    C66xx_0: GEL Output:  DIEID0 ---> 0x0F008010
    C66xx_0: GEL Output:  DIEID1 ---> 0x0404276B
    C66xx_0: GEL Output:  DIEID2 ---> 0x00000000
    C66xx_0: GEL Output:  DIEID3 ---> 0x3A480021
    C66xx_0: GEL Output:  ********************************** C6678 MACID Register (MACID) ************************************
     
    C66xx_0: GEL Output:  MACID[31:0] ---> 0x4C189859
    C66xx_0: GEL Output:  MACID[32:47] ---> 0xB499
    C66xx_0: GEL Output:  BCAST[16](Broadcast Reception) ---> Broadcast
    C66xx_0: GEL Output:  BCAST[17](MAC Flow Control) ---> Off
    C66xx_0: GEL Output:  CHECKSUM[24:31] ---> 0x85

    I will probe the i2c line and update you.


    Regards,

    S.Sivanantham

  • 0 in reply to Sivanantham S
    TI__Guru** 116830 points
    The boot strap pins appear to be correctly configured to read from I2C address 0x50 but you didn`t indicate the location of the Program counter .
  • 0 in reply to Rahul Prabhu
    Intellectual 840 points

    Hi,

    The location of PC is 0x800340.  I checked PC by loading sample code thro blakhawk 560v2  system trace.

    Is it correct method to see PC?

    Regards,

    S.Sivanantham

  • 0 in reply to Sivanantham S
    TI__Guru** 116830 points
    Sivanantham,

    When you run the Debug GEL file, it should read the PC. The other way is to read the way you have using the emulator connection to the core.

    The value you are reporting is strange as the ROM code shouldn`t be executing in this region for I2C boot on the the device. Can you please copy the Debug GEL log to a file and attach it here for complete view of your system setup.

    How many boards have you tested this on and did you try this image on the EVM before trying this on your custom board?

    Regards,
    Rahul
  • 0 in reply to Rahul Prabhu
    Intellectual 840 points

    Hi,

    I burned the image in another EEPROM whose address is 0x51 and tried booting. It boots successfully.

    The same procedure is not working in EEPROM (0x50).

    Is there anything wrong in my conversion process ?

    P.S : EEPROM address is changed in boot mode accordingly

    Kindly

    Regards,

    S.Sivanantham