I have two different development kits for the DM6446. The first is running the old MontaVista 2.6.10 on a 3rd party demo board.
The second is running using the PSP 3.0.1 (linux 2.6.32) from the Arago project running on the DVM-6446.
On the first 2.6.10 I can get a sustanted write speed of about 20 MBps using a JFS filesystem. One the second (2.6.32) I can get peak 20 MBps, however it flucuates all over the place dropping down to 8MBps some times). This is all using UDMA Mode 4, the highest the davinci 6446 supports.
With that being said I have dived deep into this problem looking at the differences between the palm chip drivers. There are quite a few changes so I decided to hook up a logic analyzer to the the DMA signaling lines.
Now bear with me while I talk low level. On the ATA interface the DMARQ line signals to the host that the device is ready to receive data. Sometime during a large file transfer the DDMARDY asserts telling the host that the drive needs to pause communication. The ATA specification says that the device will eventually de-assert DDMARDY when its ready to receive more data. There is an additional STOP line that the host can assert to tell the device that it is done sending data or terminate.
Now here is what I am seeing. On the 3d-party 2.6.10 kernel board when the DDMARDY line asserts (telling the host to wait), the host stops sending data and waits, but after about 200 uS I see the STOP line assert and de-assert, then it toggles 8 times and another 50 uS laters it toggles again and the DMARQ line from the device finally goes high saying more data can be transferred. This scenario is presented exactly the same on the EVM-6446 however instead of ~200uS before the STOP line from the host starts toggeling, its more like 8millseconds!
This is quite puzzling to me, first why does the host even initiate a STOP when the device told it to pause, and second what is controlling this sort of timeout? I've looked through all the registers in the ATA spru document and I didn't see anything related to a timeout. There doesn't seem to be anything on the ATA specification that says a host should stop the DMA burst out when it has waited for too long.
Any thoughts? I'm pretty sure that this is the cause for slower write speeds on the newer kernel or this EVM board.
Thanks in advance