AM5728: PCIe layout

Kevin Shia

Part Number: AM5728
Other Parts Discussed in Thread: CDCM9102,

Hello,

I am wondering how the PCIe layout should be implemented on AM5728. Based on previous discussions with engineers, I know that we have to use the CDCM9102 100 MHz clock generator to create a clock for AM5728 and the device. My question is how should it be routed? If the data line from the device to AM5728 is X length long, what should the clock lengths be?

Attached is an image to describe what I am asking.

Regards,

Kevin

over 7 years ago

0 Biser Gatchev-XID over 7 years ago

TI__Guru**** 393215 points

Hi,

You can find design recommendations in sections 8.3 and 8.7 of the AM572x Datasheet SR2.0 Rev. C. Additionally you can use the AM572x GP EVM board layout file for reference: http://www.ti.com/tool/TMDSEVM572X#Technical Documents

0 B.C. over 7 years ago in reply to Biser Gatchev-XID

TI__Genius 16275 points

There is no need to match clock and data lengths. While not critical, I would recommend roughly matching the lengths of the two clock traces, from the clock generator to the SoCs. This will minimize the jitter phase difference between the SoCs.

0 Kevin Shia over 7 years ago in reply to B.C.

Prodigy 140 points

Hey Biser,

When you mean matching the lengths of the two clock traces, do you mean, PCIE_CLOCK1 = PCIE_CLOCK2 = DATA?

Or do you mean PCIE_CLOCK1 + PCIE_CLOCK2 = DATA?

Thanks,

Kevin

0 B.C. over 7 years ago in reply to Kevin Shia

TI__Genius 16275 points

PCIE_CLOCK1 = PCIE_CLOCK2

No need to match DATA length to CLOCK length. Also, the clock matching recommendation above is not required, but could be helpful in some cases.

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AM5728: PCIe layout