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TMS320C6748: RSCTRL in PLL

Part Number: TMS320C6748

I ran across RSTYPE and RSCTRL while debugging another problem and the only mention of them is in the Technical Reference manual under the PLL registers.  What is the difference between an external reset (pull reset line low) and setting the SWRST bit in the RSCTRL register?  Also, what happens if the watchdog dog timer sets off a reset - what is the value of RSTYPE?

Thanks!

Mike

  • Hi Mike,

    Also, what happens if the watchdog dog timer sets off a reset - what is the value of RSTYPE?

    This is explained in Data Manual (section 6.4.1 Power-On Reset (POR)):
    CAUTION: A watchdog reset triggers a POR.
    So, the RSTYPE will indicated a POR => [bit 0]POR = 0x1

    The reset initiated by RSCTRL is a software reset, while the external reset is a hardware reset. The external reset is described in Data Manual: Section 3.7.1 Device Reset, NMI and JTAG and Section 6.4 Reset.

    Best Regards,
    Yordan
  • Thank you.  That explains a lot. 

    Mike