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TMS320DM6446: how ROM BOOT LOADER is invoked at power on in dm6446?

nirav parmar13
Prodigy 120 points
Part Number: TMS320DM6446

I was trying to understand the bootup sequence for the da vinci dm6446 SoC.

Can someone please help me understand how the boot up happens, as 
we need a non-volatile memory at the reset vector location(DM6446 RAM at addreess 0x00000000). So how does the control reach the ROM 
boot loader(RBL) which is at starting address 0x00004000 . Do we have some kind of remap of memory map 
happenning here.

  • 0 in reply to Pavel Botev
    Prodigy 120 points
    hey,i already read that data sheet and data sheet gives information about what ROM boot loader will do but how control will go to boot loader that is not given so have look at my question once again.
  • 0 in reply to nirav parmar13
    TI__Guru**** 170625 points

    Nirav,

    The code that runs immediately after a reset or power-on has to be stored on-chip in the SoC; this is known as ROM code. It is programmed into the chip when it is manufactured.

    The on-chip ROM code is where the start-up code will reside in the device. Therefore, at power-on reset, hardware must access the first instruction from internal ROM.

    U-boot is quite often not the first bootloader that executes on a processor. The first loader on TI device is a mask-programmed ROM bootloader (ROM Code) that wakes the processor up to the point where it can start u-boot. TI device has a set of physical pins that have to be strapped in hardware such that the reset vector of the processor can point at the location where this “pre-bootloader” lives.

    The DM64x reset vector is at address 0x00004000, this is where ROM Code start. One exception is when BTSEL[1:0] pins are configured for "ARM EMIFA External Boot", in this case reset vector is 0x02000000.

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Prodigy 120 points
    It's bit wrong information,
    You said that reset vector address in case of dm6446 is at 0x00004000 but it's not ,reset vector address is 0x00000000 ,which is ram location and before resetting arm opecode of branch to ROM's starting location is written by some module of soc and then arm is reset so after reset it will try to fetch very first Instruction from ram location 0x00000000 that is branch to ROM bootloader at 0x00004000.
    I have tested it with debugger connected to ccs and seen memory on system reset.
    Any corrections from your side in this explanation is appreciated



    Thank you ,
    Nirav
  • 0 in reply to nirav parmar13
    TI__Guru**** 170625 points

    Nirav,

    nirav parmar13 said:
    You said that reset vector address in case of dm6446 is at 0x00004000 but it's not

    This is stated in DM64x TRM, section 12.1 Boot Modes Overview

    After reset (POR, warm reset, or max reset), ARM program execution begins in ARM ROM at 0000:4000h, except in the case of a GP (General Purpose) device and BTSEL[1:0] = 01, indicating a NOR Boot.

    I suspect that when you are using JTAG debugger to connect to ccs, you are in a special emulation/debug mode, where the reset vector is pointing to TCM IRAM0 start address, see DM64x TRM, section 3.7 Tightly Coupled Memory

    Another possible explanation is that the code located at 0x00000000 is checking BTSEL[1:0] pins value, and based on the value it jumps to 0x00004000 or 0x02000000). Thus you have reset vector of 0x00000000 in all the op modes (debug and normal modes), see DM64x TRM, section 11.4.3 ARM Boot Mode Configuration

    The BTSEL[1:0] inputs determine whether the ARM will boot from its ROM or from the Asynchronous EMIF (AEMIF). When ROM boot is selected (BTSEL[1:0] = 00, 10, or 11), a jump to the internal ROM (0000:4000h) is forced into the first fetched instruction word. The embedded ROM boot loader code (RBL) then performs certain configuration steps, reads the BOOTCFG register to determine the desired boot method, and branches to the appropriate boot function (that is, a NAND Flash loader utility or UART loader utility). If AEMIF boot is selected (BTSEL[1:0] = 01), a jump to the lowest AEMIF address (0200:0000h) is forced into the first fetched instruction word. The ARM then continues executing from external memory using the default AEMIF timings until modified by software

     

    Regards,
    Pavel