TMS320C6657: Problem with PDK I2C driver when using MSMCSRAM

Hi Rahul,

Yes, I understand it's just a library and gets placed by the user, however I was hoping that the library code at runtime uses some portion of MSMCSRAM for purpose of synchronization of driver use in a multi-core envorinment, which would explain the colission with IPC. I understand from your comment that this is not so. I will try to describe my usage of I2C driver and IPC further:

My project utilizes both I2C driver + OSAL from PDK, and the IPC RTSC module.

By default my Platform places code, data and stack sections in DDR3, so the I2C driver is allocaed to the DDR. Regarding MSMCSRAM, the whole MSMCSRAM is used by the IPC:

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From .map file:

ti.sdo.ipc.SharedRegion_0

* 0 0c000000 00100000 NOLOAD SECTION

0c000000 00100000 --HOLE--

This is same on both .map files for both cores.

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From .cfg File:

var Ipc = xdc.useModule('ti.sdo.ipc.Ipc');

var Notify = xdc.useModule('ti.sdo.ipc.Notify');

var HeapBufMP = xdc.useModule('ti.sdo.ipc.heaps.HeapBufMP');

var GateHWSem = xdc.useModule('ti.sdo.ipc.gates.GateHWSem');

var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');

Ipc.procSync = Ipc.ProcSync_ALL;

var nameList = MultiProc.getDeviceProcNames();

MultiProc.setConfig(null, nameList);

/* To avoid wasting shared memory for MessageQ transports */

for (var i = 0; i < MultiProc.numProcessors; i++) {

Ipc.setEntryMeta({

remoteProcId: i,

setupMessageQ: false,

// setupNotify: true,

});

}

/* Shared Memory base address and length */

var SHAREDMEM = 0x0C000000;

var SHAREDMEMSIZE = 0x00100000;

/*

* Need to define the shared region. The IPC modules use this

* to make portable pointers. All processors need to add this

* call with their base address of the shared memory region.

* If the processor cannot access the memory, do not add it.

*/

var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');

SharedRegion.setEntryMeta(0,

{ base: SHAREDMEM,

len: SHAREDMEMSIZE,

ownerProcId: 0,

cacheEnable: true,

cacheLineSize: 128,

isValid: true,

// createHeap: true,

name: "MSMCSRAM_0",

});

This .cfg code is used by both core0 project and core1 project.

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Everything worked fine and I had IPC communication until I decided to use I2C driver and OSAL of the PDK.

Regarding the I2C driver and OSAL, in .map file I see that everythihng is placed in the DDR3 memory.

I2C_init(),

I2C_Params_init(&pHandle->i2cParams),

pHandle->i2cHandle = I2C_open(I2C_INSTANCE, &pHandle->i2cParams),

I run no OSAL init functions or anything, maybe this could be a problem??????????????

These functions above are run at the main(), before BIOS_start() on both cores.

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#define INTERRUPT_LINE 0

#define MSG_EVENT_ID 10

#define ACK_EVENT_ID 11

#define PLS_EVENT_ID 12

#define MSW_EVENT_ID 13

Ipc_start()

Notify_registerEvent(pObject->destCorNum, INTERRUPT_LINE, MSG_EVENT_ID,

(Notify_FnNotifyCbck)ipc_msg_arrived_cb, NULL)

Notify_registerEvent(pObject->destCorNum, INTERRUPT_LINE, ACK_EVENT_ID,

(Notify_FnNotifyCbck)ipc_ack_arrived_cb, NULL)

Notify_registerEvent(pObject->destCorNum, INTERRUPT_LINE, PLS_EVENT_ID,

(Notify_FnNotifyCbck)ipc_pls_arrived_cb, NULL)

Notify_registerEvent(pObject->destCorNum, INTERRUPT_LINE, MSW_EVENT_ID,

(Notify_FnNotifyCbck)ipc_msw_arrived_cb, NULL)

These above are also run before BIOS_start(), but after the I2C inits and opens on both cores.

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The folliwing code is run on both cores then:

/*create/use heap*/

if (pObject->selfCorNum == 0) {

/*

* Create the heap that will be used to allocate memory.

*/

HeapBufMP_Params_init(&pObject->heapBufParams);

pObject->heapBufParams.regionId = 0;

pObject->heapBufParams.name = HEAP_NAME;

pObject->heapBufParams.numBlocks = 2;

pObject->heapBufParams.blockSize = HEAP_BUF_SIZE;

pObject->heapHandle = HeapBufMP_create(&pObject->heapBufParams);

if (pObject->heapHandle == NULL) {

System_abort("HeapBufMP_create failed\n" );

}

}

else {

/* Open the heap created by the other processor. Loop until opened. */

do {

status = HeapBufMP_open(HEAP_NAME, &pObject->heapHandle);

/*

* Sleep for 1 clock tick to avoid inundating remote processor

* with interrupts if open failed

*/

if (status < 0) {

Task_sleep(1);

}

} while (status < 0);

}

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What I see is that if I remove HeapBufMP_create(&pObject->heapBufParams); from my code above, the I2C driver then operates well. But if this function runs then the I2C driver malfunctions.

On the first transfer on I2C the SCL line gets held on constant LOW and further uses of the driver result in endless blocking.

I'm trying to understand how HeapBufMP_create could cause a problem on the I2C driver.

Maybe there is a collision on OSAL level?? or on the multiprocessor signalings that sync i2c/ipc operations?

Was I required to perform inits of the OSAL library of PDK? Maybe the inits before BIOS_start cause problems?

Awaiting your kind help...

Regards

Alex

P.S. There are no overlapping sections between cores except for MSMCSRAM for IPc purposes.

Also, I use two Platform definitions, on each one of them the code,memory and stack sections are mapped to separate halves of the DDR.