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AMIC110: EtherCAT shared memory question

Evan Chang67
Prodigy 40 points
Part Number: AMIC110
Other Parts Discussed in Thread: AM4379, AM3359

AMIC110 and PRU-ICSS-EtherCAT_Slave use the shared memory to save the EtherCAT Registers, and both of them can read/write it. 

Can they read or write the register simultaneous or not? If not allow, how to avoid this situation? Use EtherCAT Sync Management Setting or RTOS already avoid it?

Thanks for respond.

  • 0
    TI__Guru**** 393215 points
    The RTOS team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Expert 7570 points
    Hi

    The PRU-ICSS registers can be read by both the ARM and the PRU without conflict at the hardware level.
    At the EtherCAT slave application level, the EtherCAT Sync manager coordinates the register access.
    The example code Illustrates the EtherCAT slave operation.
    Are you working PRU-ICSS-EtherCAT_Slave_01.00.04.02 ?
    If so is the application that you are working with ethercat_slave_full or ecat_ti_esc_spi_slave?

    David
  • 0 in reply to David Zaucha
    Prodigy 40 points

    Hi

    Now I am working with ethercat_slave_demo example.

    In my case, I want to run the EtherCAT application in AMIC110 and without other processor.

    I need to sure that there is no problem in read/write shared memory simultaneous.

    Are you avoid this situation at hardware level or RTOS level ? May AMIC110 can read/write the shared memory without RTOS? Or PRU-ICSS-EtherCAT_Slave need use with RTOS.

    Thanks for your respond.

  • 0 in reply to Evan Chang67
    TI__Expert 7570 points
    Hi

    I apologize for the delay. I have a question in to the design team on the EtherCAT and full EtherCAT example on the AMIC110 board. I should be able to reply very shortly.

    David
  • 0 in reply to David Zaucha
    TI__Expert 7570 points

    Hi

    I apologize for the delay.

    The access control is performed by a combination of firmware and ARM software .

    The EtherCAT example program illustrates a 32 bit read and a write operation to an EtherCAT slave. These sequences permit simultaneous operation without collisions. 

    On the AM335x ICEV2 and AM437x IDK a write sets GPIO which drive 8 LEDs on the board.  Similarly on the AM335x ICEV2 and AM437x IDK the read will read 8 GPIOs that can be set on the expansion header.

    The AMIC110 ICE board is a hardware optimized configuration to show how the AMIC110 can be used to perform support a low cost SPI interface to a MCU like a C2000. Unfortunately the AMIC110 Industrial Communications Engine (ICE) EVM does not have 8 GPIO Inputs and 8 LED displays like the AM3359 ICE and AM4379 IDK. This makes it a little more difficult by not having these interfaces to observe the operations of the EtherCAT APIs in supporting EtherCAT communications.   The AMIC110 and AM335x ICEV2 are members of the same family. You may want to consider using an AM3359 Industrial Communications Engine ( http://www.ti.com/tool/tmdsice3359 ) for initial development and then transition to an AMIC110 ICE .

    The Industrial SDK EtherCAT slave implementation is integrated with EtherCAT Slave Stack Code (SSC) ET9300.

    The Industrial SDK EtherCAT example has a limited configurability and exposes only limited implementation of the third party stack with a limited set of capabilities. Features such as object dictionary adaptation is not possible in this evaluation version. In this example, the example application source code is provided source, however the EtherCAT stack is only provided in object format.  This limited feature example is useful for simple evaluations of EtherCAT performance.  

    For development the full feature application provides the stack code and examples and permits modification the operation of the change the slave configuration and operation.  The full featured application requires complete stack source, SSC 5.11 source code, from ETG website. 

    The build the full featured EtherCAT Industrial example it is necessary to patch Beckhoff Slave Stack Code  and build the application as described in http://processors.wiki.ti.com/index.php/PRU_ICSS_EtherCAT#Building_full_feature_EtherCAT_Slave_Application

    Documentation on ET9300 is available at https://download.beckhoff.com/download/document/io/ethercat-development-products/an_et9300_v1i7.pdf. This description is applicable for the TI EtherCAT Slave Controller since any differences in hardware platforms are abstracted by the stack HAL layer. For additional questions and support on SSC5.11 and ET9300 customers should use the EtherCAT ETG forums.

    The Sitara FAQ which is available at http://processors.wiki.ti.com/index.php/FAQ_Sitara_Industrial has some additional information on EtherCAT and PRU-ICSS-Industrial software development and applications which may be of assistance.

     

    David