Hi,
a customer observes that a delay needs to be inserted in order to extend the RESET pulse low to the DDR device. The customer is currently using 40ms which works for most boards, but some boards with different memory vendor requires 60ms. We are trying to rootcause this.
I am trying to resolve whether what TI's official answer is on
[] RESET low pulse duration
[] RESET high to CKE timing (JEDEC require 600us)
Below is a more inconclusive thread about the 600us. In some u-boot patches discussed I see that topic, however the official TI u-boot 2016.05 does not seem the RESET to CKE delay be implemented.
RESET to CKE
u-boot code for 2016.05 as an example
Based on our extensive design experience with the AM335x, what delays need to be inserted to be compliant with JEDEC as well as be robust for all DDR vendors?
What are the root-causes for having to extend the RESET low pulse?
Thanks,
--Gunter
