Starterware/TDA3: DPLL setting with 27MHz input for SYS_CLK1

Taro Shibata

Expert 8010 points

Part Number: TDA3

Tool/software: Starterware

Hi experts,

I have a query about SYS_CLK1 on TDA3x.

ON TDA3x EVM, 20 MHz crystal is mounted for SYS_CLK1 input.

If we want to replace it with 27 MHz, we need to change sysboot[9:8] setting from 0b01 to 0b10.

In addition to this, we also need to change all 5 DPLL configuration so that each blocks get appropriate frequency of input clocks.

I would like to achieve this with minimum effort.

The idea is to modify only N, M in DPLL_xxx to get the same frequency for CLKOUT.

Could you please review if below M, N settings are fine or not?

Original setting (SYS_CLK1: 20 MHz)

	DPLL_CORE	DPLL_PER	DPLL_EVE_VID_DSP	DPLL_GMAC_DSP	DPLL_DDR
Ref Clock (MHz)	20	20	20	20	20
N	4	4	7	4	4
M	266	192	238	250	266
CLKOUT (MHz)	1064	768	595	1000	1064

New setting (SYS_CLK1: 27 MHz)

	DPLL_CORE	DPLL_PER	DPLL_EVE_VID_DSP	DPLL_GMAC_DSP	DPLL_DDR
Ref Clock (MHz)	27	27	27	27	27
N	26	26	26	26	26
M	1064	768	595	1000	1064
CLKOUT (MHz)	1064	768	595	1000	1064

Thanks & Regards,

-Shibata

over 7 years ago

0 Mariya Petkova over 7 years ago

TI__Expert 4885 points

Hi, Taro Shibata,

You can use Clock tree tool to check your settings. You can download it from here:

Regards,

Mariya

0 Taro Shibata over 7 years ago in reply to Mariya Petkova

TI__Expert 8010 points

Hi Mariya,

Thanks for your prompt reply.

Yes, I already verified these settings with Clock Tree Tool, no error found with Frequency Analyzer.
It look like I can get expected clocks by these settings.

I wonder if there are any points to be taken care of/overlooked on this.
Please let me know your thought.

Thanks,
-Shibata

0 Piyali Goswami over 7 years ago in reply to Taro Shibata

TI__Mastermind 30245 points

Hi Shibata-san,

The values for M and N that you have used are okay.

There are some general limitations for the M and N Values.

REFCLK = CLKINP/(N+1). should be within a given range.

DCOCLK = CLKINP × [M/(N+1)] should be within a given range.

Both these conditions are met by your configurations.

Thanks and Regards,

Piyali

0 Stanislav Stilyanov over 7 years ago in reply to Taro Shibata

TI__Genius 17720 points

Hi Shibata-san,
I'm sorry, I don't know for PLL settings.
I recall that one problem with a 27 MHz clock, is that the 32-k clock is a divided version of SYS_CLK1 clock, therefore 32-k will run faster too. Please see if you are using any modules (I think they are only timers, RTI, and Counter32k, and GPIO for debounce function) with 32-k clock in your software.
If no module is using 32-k clock then it is fine (regarding the 32k clock).
If at least one module is using 32-k clock, then software must be revised to 'know' the difference.

Best regards,
Stan

0 Taro Shibata over 7 years ago in reply to Piyali Goswami

TI__Expert 8010 points

Hi Piyali,

Thanks for your comments.

Regards,

-Shibata

0 Taro Shibata over 7 years ago in reply to Stanislav Stilyanov

TI__Expert 8010 points

Hi Stan,

Thank you for pointing that out.
I will check if FUNC_32K_CLK is used or not.

Regards,
-Shibata

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Starterware/TDA3: DPLL setting with 27MHz input for SYS_CLK1