Linux/AM5718: Error when running OpenCL example

Darth Vader

Part Number: AM5718

Tool/software: Linux

Howdy,

On a custom board with a Sitara AM57X, I obtain, from the board's /var/log/messages, this following error: "user.err kernel: [ 234.723032] edma 43300000.edma: dma_ccerr_handler: Error interrupt without error event!".

This error happens when I run a OpenCL example provided by the ti-processor-sdk-linux-rt-am57xx-evm-03.02.00.05-Linux-x86 simultaneously with a UART data exchange.

In same time when the error occurs, I observe UART console definitively freezing, it is still possible to connect to the board with a ssh console.

I have investigated on this. In the source code, the error comes from kernel-source/drivers/dma/edma.c : static irqreturn_t dma_ccerr_handler(int irq, void *data). By instrumentation in this code source, now I know this error is generated by the "edma3_ccerrint" interrupt. But I don't not why. I have read some part çof the datasheet, but I find nothing to start a trace.

Since this point, I'm blocked. Have you some ideas to solve this error or improve knowlegdes about it?

over 7 years ago

0 Yordan Kovachev over 7 years ago

TI__Guru**** 161600 points

Hi,

Can you please post the whole log from /var/log/messages or your dmesg log?

Best Regards,
Yordan

0 Darth Vader over 7 years ago in reply to Yordan Kovachev

Prodigy 50 points

Hello,

Output from dmesg in attachment

Fullscreen log_dmesg_to_TI.txt Download

~# dmesg
[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.4.32-rt41+ (XXXXXXXX) () #2 SMP PREEMPT Tue Sep 19 12:00:00 CEST 2017
[    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=10c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[    0.000000] Machine model: TI AM5718 XXXXXXXX XXXXXXXX
[    0.000000] Reserved memory: created CMA memory pool at 0x99000000, size 64 MiB
[    0.000000] Reserved memory: initialized node dsp1_cma@99000000, compatible id shared-dma-pool
[    0.000000] cma: Reserved 24 MiB at 0x9e400000
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] OMAP4: Map 0x9fe00000 to fe600000 for dram barrier
[    0.000000] On node 0 totalpages: 108032
[    0.000000] free_area_init_node: node 0, pgdat c15f5b40, node_mem_map de000000
[    0.000000]   Normal zone: 1024 pages used for memmap
[    0.000000]   Normal zone: 0 pages reserved
[    0.000000]   Normal zone: 108032 pages, LIFO batch:31
[    0.000000] DRA722 ES1.0
[    0.000000] PERCPU: Embedded 12 pages/cpu @dfd69000 s18176 r8192 d22784 u49152
[    0.000000] pcpu-alloc: s18176 r8192 d22784 u49152 alloc=12*4096
[    0.000000] pcpu-alloc: [0] 0
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 107008
[    0.000000] Kernel command line: console=none root=/dev/ram0 rw
[    0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes)
[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
[    0.000000] Memory: 314900K/432128K available (4467K kernel code, 202K rwdata, 1332K rodata, 16456K init, 169K bss, 27116K reserved, 90112K cma-reserved, 0K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
[    0.000000]     vmalloc : 0xe0800000 - 0xff800000   ( 496 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xe0000000   ( 512 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc05b1fec   (5800 kB)
[    0.000000]       .init : 0xc05b2000 - 0xc15c4000   (16456 kB)
[    0.000000]       .data : 0xc15c4000 - 0xc15f6a40   ( 203 kB)
[    0.000000]        .bss : 0xc15f6a40 - 0xc16211b4   ( 170 kB)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000]  Build-time adjustment of leaf fanout to 32.
[    0.000000]  RCU restricting CPUs from NR_CPUS=2 to nr_cpu_ids=1.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=1
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] ti_dt_clocks_register: failed to lookup clock node gmac_gmii_ref_clk_div
[    0.000000] OMAP clockevent source: timer1 at 32786 Hz
[    0.000000] Architected cp15 timer(s) running at 6.14MHz (virt).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 440795202250 ns
[    0.000006] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns
[    0.000021] Switching to timer-based delay loop, resolution 162ns
[    0.000550] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
[    0.000560] OMAP clocksource: 32k_counter at 32768 Hz
[    0.001088] Console: colour dummy device 80x30
[    0.001114] Calibrating delay loop (skipped), value calculated using timer frequency.. 12.29 BogoMIPS (lpj=61475)
[    0.001132] pid_max: default: 32768 minimum: 301
[    0.001223] Security Framework initialized
[    0.001265] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.001278] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.001859] CPU: Testing write buffer coherency: ok
[    0.002118] /cpus/cpu@0 missing clock-frequency property
[    0.002136] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.002190] Setting up static identity map for 0x80008280 - 0x800082d8
[    0.060171] Brought up 1 CPUs
[    0.060186] SMP: Total of 1 processors activated (12.29 BogoMIPS).
[    0.060196] CPU: All CPU(s) started in SVC mode.
[    0.061409] devtmpfs: initialized
[    0.110098] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
[    0.111651] omap_hwmod: l3_main_2 using broken dt data from ocp
[    0.381524] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.383371] pinctrl core: initialized pinctrl subsystem
[    0.384451] NET: Registered protocol family 16
[    0.386120] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.410543] cpuidle: using governor ladder
[    0.440583] cpuidle: using governor menu
[    0.453185] OMAP GPIO hardware version 0.1
[    0.481934] omap-gpmc 50000000.gpmc: could not find pctldev for node /ocp/l4@4a000000/scm@2000/pinmux@1400/gpmc_pins_default, deferring probe
[    0.488488] omap4_sram_init:Unable to allocate sram needed to handle errata I688
[    0.488503] omap4_sram_init:Unable to get sram pool needed to handle errata I688
[    0.488770] OMAP DMA hardware revision 0.0
[    0.577668] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver (LinkedList1/2/3 supported)
[    0.579046] edma 43300000.edma: memcpy is disabled
[    0.586703] edma 43300000.edma: TI EDMA DMA engine driver
[    0.591687] omap-iommu 40d01000.mmu: 40d01000.mmu registered
[    0.591909] omap-iommu 40d02000.mmu: 40d02000.mmu registered
[    0.592104] omap-iommu 58882000.mmu: 58882000.mmu registered
[    0.592758] SCSI subsystem initialized
[    0.593407] pps_core: LinuxPPS API ver. 1 registered
[    0.593420] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.593454] PTP clock support registered
[    0.601871] clocksource: Switched to clocksource arch_sys_counter
[    0.616725] NET: Registered protocol family 2
[    0.617431] TCP established hash table entries: 4096 (order: 2, 16384 bytes)
[    0.617482] TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
[    0.617567] TCP: Hash tables configured (established 4096 bind 4096)
[    0.617628] UDP hash table entries: 256 (order: 1, 8192 bytes)
[    0.617657] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[    0.617850] NET: Registered protocol family 1
[    7.127373] futex hash table entries: 256 (order: 2, 16384 bytes)
[    7.145344] VFS: Disk quotas dquot_6.6.0
[    7.145565] VFS: Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[    7.147324] jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
[    7.153044] NET: Registered protocol family 38
[    7.153115] io scheduler noop registered
[    7.153134] io scheduler deadline registered
[    7.153342] io scheduler cfq registered (default)
[    7.158616] pinctrl-single 4a003400.pinmux: 282 pins at pa fc003400 size 1128
[    7.158746] pinctrl-single 4a002e8c.pinmux: 1 pins at pa fc002e8c size 4
[    7.165592] Serial: 8250/16550 driver, 10 ports, IRQ sharing disabled
[    7.170002] 4806a000.serial: ttyS0 at MMIO 0x4806a000 (irq = 299, base_baud = 3000000) is a 8250
[    7.170962] 48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 300, base_baud = 3000000) is a 8250
[    7.183498] brd: module loaded
[    7.271049] loop: module loaded
[    7.272446] mtdoops: mtd device (mtddev=name/number) must be supplied
[    7.273367] libphy: Fixed MDIO Bus: probed
[    7.321911] davinci_mdio 48485000.mdio: davinci mdio revision 1.6
[    7.321928] davinci_mdio 48485000.mdio: detected phy mask fffffff7
[    7.338850] libphy: 48485000.mdio: probed
[    7.338872] davinci_mdio 48485000.mdio: phy[3]: device 48485000.mdio:03, driver unknown
[    7.348617] cpsw 48484000.ethernet: Detected MACID = 98:84:e3:67:c9:72
[    7.348826] cpsw 48484000.ethernet: cpts: overflow check period 800
[    7.349898] cpsw 48484000.ethernet: cpsw: Detected MACID = 98:84:e3:67:c9:73
[    7.350710] i2c /dev entries driver
[    7.351560] omap-aes 4b500000.aes: OMAP AES hw accel rev: 3.3
[    7.352677] omap-aes 4b700000.aes: OMAP AES hw accel rev: 3.3
[    7.353266] omap-des 480a5000.des: OMAP DES hw accel rev: 2.2
[    7.354716] omap-sham 4b101000.sham: hw accel on OMAP rev 4.3
[    7.357824] Initializing XFRM netlink socket
[    7.357865] NET: Registered protocol family 17
[    7.357933] NET: Registered protocol family 15
[    7.357987] omap_voltage_late_init: Voltage driver support not added
[    7.358342] Power Management for TI OMAP4+ devices.
[    7.358636] ThumbEE CPU extension supported.
[    7.358664] Registering SWP/SWPB emulation handler
[    7.370351] omap-gpmc 50000000.gpmc: GPMC revision 6.0
[    7.370370] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
[    7.372130] pbias_mmc_omap5: disabling
[    7.372615] Warning: unable to open an initial console.
[    7.388417] Freeing unused kernel memory: 16456K (c05b2000 - c15c4000)
[    7.442309] CMEMK module: reference Linux version 4.4.32
[    7.443119] cmemk initialized
[    7.465484] spi_slave_rx: size of buffers = 7508 bytes
[    7.465499] spi_slave_rx: number of buffers = 16
[    7.472091] [mcspi_probe] MCSPI device's OF node is /ocp/spi@480b8000
[    7.472109] [mcspi_probe] targeted controller is MCSPI3
[    7.472124] [mcspi_probe] match device compatible attribute is: ti,omap4-mcspi
[    7.472135] [mcspi_probe] bus_num=3, pdev_name=480b8000.spi
[    7.472162] [mcspi_probe] MCSPI3 controller's attributes: @phys=0x480b8000, @virt=0xfa0b8000
[    7.472212] [mcspi_slave_setup] perform a soft reset of the MCSPI controller...
[    7.472225] [mcspi_check_clock_domains] clock domains are OK
[    7.474491] [mcspi_test_rx_lines] CS0 input signal line toggles well
[    7.478387] [mcspi_test_rx_lines] SCLK input signal line toggles well
[    7.478396] [mcspi_test_rx_lines] D1 input signal line toggles well
[    7.478548] mcspi_slave_rx 480b8000.spi: registered slave rx spi_slave_rx3
[    7.483798] [YYYYYYYY_init]: YYYYYYYY driver successfully registered
[    7.483829] bus for spi_slave_rx is spi_slave_rx3.0
[    7.484003] spi_slave_rx spi_slave_rx3.0: setup mode 0, 16 bits/w, 30000000 Hz max --> 1
[    7.484335] YYYYYYYY spi_slave_rx3.0: driver probed
[    7.484585] YYYYYYYY YYYYYYYY0: new device created
[    7.484640] mcspi_slave_rx 480b8000.spi: registered child spi_slave_rx3.0
[    8.542890] omap-rproc 40800000.dsp: assigned reserved memory node dsp1_cma@99000000
[    8.542983]  remoteproc0: 40800000.dsp is available
[    8.542996]  remoteproc0: Note: remoteproc is still under development and considered experimental.
[    8.543007]  remoteproc0: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
[    8.612021] omap-mailbox 48840000.mailbox: omap mailbox rev 0x400
[    8.669691] m25p80 spi32766.0: found n25q512ax3, expected n25q512a
[    8.669754] m25p80 spi32766.0: n25q512ax3 (65536 Kbytes)
[    8.669888] 9 ofpart partitions found on MTD device spi32766.0
[    8.669900] Creating 9 MTD partitions on "spi32766.0":
[    8.669914] 0x000000000000-0x000000020000 : "mtd_ZZZZZZZZ_mlo"
[    8.691267] 0x000000020000-0x0000000f0000 : "mtd_ZZZZZZZZ_uboot"
[    8.713073] 0x0000000f0000-0x000000100000 : "mtd_ZZZZZZZZ_env"
[    8.730583] 0x000000100000-0x000000bc0000 : "mtd_ZZZZZZZZ_zimage"
[    8.746602] 0x000000bc0000-0x000000c00000 : "mtd_ZZZZZZZZ_dtb"
[    8.796377] 0x000000c00000-0x000001400000 : "mtd_aml"
[    8.832805] 0x000001400000-0x000002bc0000 : "mtd_KKKKKKKK_zimage"
[    8.890922] 0x000002bc0000-0x000002c00000 : "mtd_KKKKKKKK_dtb"
[    8.928842] 0x000002c00000-0x000004000000 : "mtd_loads"
[    9.001614] omap_rng 48090000.rng: OMAP Random Number Generator ver. 20
[    9.082375] libata version 3.00 loaded.
[    9.086266] ahci 4a140000.sata: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x0 impl platform mode
[    9.086287] ahci 4a140000.sata: flags: 64bit ncq sntf pm led clo only pmp pio slum part ccc apst
[    9.161949]  remoteproc0: registered virtio0 (type 7)
[    9.167797] scsi host0: ahci
[    9.168443] ata1: DUMMY
[    9.234095]  remoteproc0: powering up 40800000.dsp
[    9.319567]  remoteproc0: Booting fw image dra7-dsp1-fw.xe66, size 22296088
[    9.327108] omap_hwmod: mmu0_dsp1: _wait_target_disable failed
[    9.327163] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0
[    9.327287] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0
[    9.344785] net eth0: initializing cpsw version 1.15 (0)
[    9.344825] net eth0: initialized cpsw ale version 1.4
[    9.344839] net eth0: ALE Table size 1024
[    9.357317]  remoteproc0: remote processor 40800000.dsp is now up
[    9.376793] virtio_rpmsg_bus virtio0: rpmsg host is online
[    9.376878] virtio_rpmsg_bus virtio0: creating channel rpmsg-proto addr 0x3d
[    9.401407] NET: Registered protocol family 41
[    9.422175] net eth0: phy found : id is : 0x0
[    9.422350] cpsw-phy-sel 4a002554.cpsw-phy-sel: RMII External clock is not supported
[    9.469953] net eth1: initializing cpsw version 1.15 (0)
[    9.552062] net eth1: phy found : id is : 0x0
[    9.552230] cpsw-phy-sel 4a002554.cpsw-phy-sel: RMII External clock is not supported
[    9.750827] nand: nand_decode_bbm_options: mtd->writesize=8192
[    9.750843] nand: nand_decode_bbm_options: chip->options=0x00010200
[    9.750854] nand: nand_decode_bbm_options: chip->badblockpos=NAND_LARGE_BADBLOCK_POS
[    9.750866] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x68
[    9.750876] nand: Micron MT29F32G08ABAAAWP
[    9.750887] nand: 4096 MiB, SLC, erase size: 1024 KiB, page size: 8192, OOB size: 448
[    9.750902] omap2-nand 8000000.nand: xfer_type=0
[    9.751003] omap2-nand 8000000.nand: ecc_opt=6
[    9.751011] using OMAP_ECC_BCH16_CODE_HW ECC scheme
[    9.751068] 1 ofpart partitions found on MTD device 8000000.nand
[    9.751078] Creating 1 MTD partitions on "8000000.nand":
[    9.751094] 0x000000000000-0x000100000000 : "mtd_nand"
[   10.607530] ubi0: attaching mtd9
[   11.422164] cpsw 48484000.ethernet eth0: Link is Up - 10Mbps/Full - flow control off
[   11.551980] cpsw 48484000.ethernet eth1: Link is Up - 100Mbps/Full - flow control off
[   18.884985] ubi0: scanning is finished
[   18.900616] ubi0: attached mtd9 (name "mtd_nand", size 4096 MiB)
[   18.900634] ubi0: PEB size: 1048576 bytes (1024 KiB), LEB size: 1032192 bytes
[   18.900647] ubi0: min./max. I/O unit sizes: 8192/8192, sub-page size 8192
[   18.900658] ubi0: VID header offset: 8192 (aligned 8192), data offset: 16384
[   18.900669] ubi0: good PEBs: 4094, bad PEBs: 2, corrupted PEBs: 0
[   18.900679] ubi0: user volume: 2, internal volumes: 1, max. volumes count: 128
[   18.900692] ubi0: max/mean erase counter: 9/4, WL threshold: 4096, image sequence number: 599161619
[   18.900702] ubi0: available PEBs: 0, total reserved PEBs: 4094, PEBs reserved for bad PEB handling: 78
[   18.902726] ubi0: background thread "ubi_bgt0d" started, PID 394
[   18.952149] UBIFS (ubi0:0): background thread "ubifs_bgt0_0" started, PID 400
[   19.201824] UBIFS (ubi0:0): recovery needed
[   19.684214] UBIFS (ubi0:0): recovery completed
[   19.684239] UBIFS (ubi0:0): UBIFS: mounted UBI device 0, volume 0, name "log"
[   19.684254] UBIFS (ubi0:0): LEB size: 1032192 bytes (1008 KiB), min./max. I/O unit sizes: 8192 bytes/8192 bytes
[   19.684269] UBIFS (ubi0:0): FS size: 94961664 bytes (90 MiB, 92 LEBs), journal size 8257537 bytes (7 MiB, 6 LEBs)
[   19.684281] UBIFS (ubi0:0): reserved for root: 4485273 bytes (4380 KiB)
[   19.684297] UBIFS (ubi0:0): media format: w4/r0 (latest is w4/r0), UUID 377E6BFF-6C2C-4596-A8C8-EB7CBAAE3344, small LPT model
[   19.712166] UBIFS (ubi0:1): background thread "ubifs_bgt0_1" started, PID 404
[   19.954877] UBIFS (ubi0:1): recovery needed
[   20.089786] omap_hwmod: mmu1_dsp1: _wait_target_disable failed
[   20.097195] omap_hwmod: mmu0_dsp1: _wait_target_disable failed
[   20.454785] UBIFS (ubi0:1): recovery completed
[   20.454810] UBIFS (ubi0:1): UBIFS: mounted UBI device 0, volume 1, name "hmfudata"
[   20.454824] UBIFS (ubi0:1): LEB size: 1032192 bytes (1008 KiB), min./max. I/O unit sizes: 8192 bytes/8192 bytes
[   20.454840] UBIFS (ubi0:1): FS size: 4025548800 bytes (3839 MiB, 3900 LEBs), journal size 33030144 bytes (31 MiB, 32 LEBs)
[   20.454852] UBIFS (ubi0:1): reserved for root: 4952683 bytes (4836 KiB)
[   20.454867] UBIFS (ubi0:1): media format: w4/r0 (latest is w4/r0), UUID B82B376D-8043-4C8E-91AF-B03DF83D46A0, small LPT model
[   20.776579] YYYYYYYY spi_slave_rx3.0: Starting reception
[   21.625329] random: nonblocking pool is initialized
[   91.017183] omap_hwmod: mmu0_dsp1: _wait_target_disable failed
[   91.017245] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0
[   91.023724] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0
[  189.908180] edma 43300000.edma: dma_ccerr_handler: Error interrupt without error event!
[  190.217053] edma 43300000.edma: dma_ccerr_handler: Error interrupt without error event!
[  190.277243] edma 43300000.edma: dma_ccerr_handler: Error interrupt without error event!

0 Yordan Kovachev over 7 years ago in reply to Darth Vader

TI__Guru**** 161600 points

Hi,

This error comes from edma.c:
if (!edma_error_pending(ecc)) {
/*
* The registers indicate no pending error event but the irq
* handler has been called.
* Ask eDMA to re-evaluate the error registers.
*/
dev_err(ecc->dev, "%s: Error interrupt without error event!\n",
__func__);
edma_write(ecc, EDMA_EEVAL, 1);
return IRQ_NONE;
}

Try returning IRQ_HANDLED instead of IRQ_NONE and see what the result will be.

Best Regards,
Yordan

0 Darth Vader over 7 years ago in reply to Yordan Kovachev

Prodigy 50 points

Hi,

I tried your last suggestion, the result log is in attachment (

Fullscreen dmesg_IRQ_HANDLED_For_TI.txt Download

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.4.32-rt41+ (XXXXXXXXXX) () #9 SMP PREEMPT Tue Sep 19 12:00:00 CEST 2017
[    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=10c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[    0.000000] Machine model: TI AM5718 YYYYYYYYYY ZZZZZZZZZZ
[    0.000000] Reserved memory: created CMA memory pool at 0x99000000, size 64 MiB
[    0.000000] Reserved memory: initialized node dsp1_cma@99000000, compatible id shared-dma-pool
[    0.000000] cma: Reserved 24 MiB at 0x9e400000
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] OMAP4: Map 0x9fe00000 to fe600000 for dram barrier
[    0.000000] On node 0 totalpages: 108032
[    0.000000] free_area_init_node: node 0, pgdat c15f5b40, node_mem_map de000000
[    0.000000]   Normal zone: 1024 pages used for memmap
[    0.000000]   Normal zone: 0 pages reserved
[    0.000000]   Normal zone: 108032 pages, LIFO batch:31
[    0.000000] DRA722 ES1.0
[    0.000000] PERCPU: Embedded 12 pages/cpu @dfd69000 s18176 r8192 d22784 u49152
[    0.000000] pcpu-alloc: s18176 r8192 d22784 u49152 alloc=12*4096
[    0.000000] pcpu-alloc: [0] 0 
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 107008
[    0.000000] Kernel command line: console=none root=/dev/ram0 rw
[    0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes)
[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
[    0.000000] Memory: 314900K/432128K available (4467K kernel code, 202K rwdata, 1332K rodata, 16456K init, 169K bss, 27116K reserved, 90112K cma-reserved, 0K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
[    0.000000]     vmalloc : 0xe0800000 - 0xff800000   ( 496 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xe0000000   ( 512 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc05b1fec   (5800 kB)
[    0.000000]       .init : 0xc05b2000 - 0xc15c4000   (16456 kB)
[    0.000000]       .data : 0xc15c4000 - 0xc15f6a40   ( 203 kB)
[    0.000000]        .bss : 0xc15f6a40 - 0xc16211b4   ( 170 kB)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000] 	Build-time adjustment of leaf fanout to 32.
[    0.000000] 	RCU restricting CPUs from NR_CPUS=2 to nr_cpu_ids=1.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=1
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] ti_dt_clocks_register: failed to lookup clock node gmac_gmii_ref_clk_div
[    0.000000] OMAP clockevent source: timer1 at 32786 Hz
[    0.000000] Architected cp15 timer(s) running at 6.14MHz (virt).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 440795202250 ns
[    0.000005] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns
[    0.000020] Switching to timer-based delay loop, resolution 162ns
[    0.000503] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
[    0.000514] OMAP clocksource: 32k_counter at 32768 Hz
[    0.001034] Console: colour dummy device 80x30
[    0.001060] Calibrating delay loop (skipped), value calculated using timer frequency.. 12.29 BogoMIPS (lpj=61475)
[    0.001078] pid_max: default: 32768 minimum: 301
[    0.001169] Security Framework initialized
[    0.001212] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.001225] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.001810] CPU: Testing write buffer coherency: ok
[    0.002071] /cpus/cpu@0 missing clock-frequency property
[    0.002090] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.002145] Setting up static identity map for 0x80008280 - 0x800082d8
[    0.060166] Brought up 1 CPUs
[    0.060181] SMP: Total of 1 processors activated (12.29 BogoMIPS).
[    0.060192] CPU: All CPU(s) started in SVC mode.
[    0.061406] devtmpfs: initialized
[    0.110094] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
[    0.111669] omap_hwmod: l3_main_2 using broken dt data from ocp
[    0.384237] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.386077] pinctrl core: initialized pinctrl subsystem
[    0.387169] NET: Registered protocol family 16
[    0.388838] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.410543] cpuidle: using governor ladder
[    0.440580] cpuidle: using governor menu
[    0.453222] OMAP GPIO hardware version 0.1
[    0.481925] omap-gpmc 50000000.gpmc: could not find pctldev for node /ocp/l4@4a000000/scm@2000/pinmux@1400/gpmc_pins_default, deferring probe
[    0.488480] omap4_sram_init:Unable to allocate sram needed to handle errata I688
[    0.488496] omap4_sram_init:Unable to get sram pool needed to handle errata I688
[    0.488766] OMAP DMA hardware revision 0.0
[    0.577762] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver (LinkedList1/2/3 supported)
[    0.579126] edma 43300000.edma: memcpy is disabled
[    0.586883] edma 43300000.edma: TI EDMA DMA engine driver
[    0.591904] omap-iommu 40d01000.mmu: 40d01000.mmu registered
[    0.592129] omap-iommu 40d02000.mmu: 40d02000.mmu registered
[    0.592324] omap-iommu 58882000.mmu: 58882000.mmu registered
[    0.592976] SCSI subsystem initialized
[    0.593619] pps_core: LinuxPPS API ver. 1 registered
[    0.593632] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.593667] PTP clock support registered
[    0.601884] clocksource: Switched to clocksource arch_sys_counter
[    0.616565] NET: Registered protocol family 2
[    0.617276] TCP established hash table entries: 4096 (order: 2, 16384 bytes)
[    0.617328] TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
[    0.617413] TCP: Hash tables configured (established 4096 bind 4096)
[    0.617475] UDP hash table entries: 256 (order: 1, 8192 bytes)
[    0.617504] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[    0.617699] NET: Registered protocol family 1
[    7.170812] futex hash table entries: 256 (order: 2, 16384 bytes)
[    7.188841] VFS: Disk quotas dquot_6.6.0
[    7.189061] VFS: Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[    7.190816] jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
[    7.196560] NET: Registered protocol family 38
[    7.196630] io scheduler noop registered
[    7.196650] io scheduler deadline registered
[    7.196857] io scheduler cfq registered (default)
[    7.202233] pinctrl-single 4a003400.pinmux: 282 pins at pa fc003400 size 1128
[    7.202368] pinctrl-single 4a002e8c.pinmux: 1 pins at pa fc002e8c size 4
[    7.209202] Serial: 8250/16550 driver, 10 ports, IRQ sharing disabled
[    7.213691] 4806a000.serial: ttyS0 at MMIO 0x4806a000 (irq = 299, base_baud = 3000000) is a 8250
[    7.214646] 48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 300, base_baud = 3000000) is a 8250
[    7.226911] brd: module loaded
[    7.314535] loop: module loaded
[    7.315897] mtdoops: mtd device (mtddev=name/number) must be supplied
[    7.316825] libphy: Fixed MDIO Bus: probed
[    7.361925] davinci_mdio 48485000.mdio: davinci mdio revision 1.6
[    7.361942] davinci_mdio 48485000.mdio: detected phy mask fffffff7
[    7.378949] libphy: 48485000.mdio: probed
[    7.378970] davinci_mdio 48485000.mdio: phy[3]: device 48485000.mdio:03, driver unknown
[    7.388703] cpsw 48484000.ethernet: Detected MACID = 98:84:e3:67:c9:72
[    7.388913] cpsw 48484000.ethernet: cpts: overflow check period 800
[    7.389995] cpsw 48484000.ethernet: cpsw: Detected MACID = 98:84:e3:67:c9:73
[    7.390815] i2c /dev entries driver
[    7.391670] omap-aes 4b500000.aes: OMAP AES hw accel rev: 3.3
[    7.392776] omap-aes 4b700000.aes: OMAP AES hw accel rev: 3.3
[    7.393378] omap-des 480a5000.des: OMAP DES hw accel rev: 2.2
[    7.394841] omap-sham 4b101000.sham: hw accel on OMAP rev 4.3
[    7.397976] Initializing XFRM netlink socket
[    7.398019] NET: Registered protocol family 17
[    7.398087] NET: Registered protocol family 15
[    7.398140] omap_voltage_late_init: Voltage driver support not added
[    7.398497] Power Management for TI OMAP4+ devices.
[    7.398793] ThumbEE CPU extension supported.
[    7.398822] Registering SWP/SWPB emulation handler
[    7.410530] omap-gpmc 50000000.gpmc: GPMC revision 6.0
[    7.410550] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
[    7.412312] pbias_mmc_omap5: disabling
[    7.412796] Warning: unable to open an initial console.
[    7.428605] Freeing unused kernel memory: 16456K (c05b2000 - c15c4000)
[    7.482642] CMEMK module: reference Linux version 4.4.32
[    7.483464] cmemk initialized
[    7.505948] spi_slave_rx: size of buffers = 7508 bytes
[    7.505962] spi_slave_rx: number of buffers = 16
[    7.512574] [mcspi_probe] MCSPI device's OF node is /ocp/spi@480b8000
[    7.512592] [mcspi_probe] targeted controller is MCSPI3
[    7.512607] [mcspi_probe] match device compatible attribute is: ti,omap4-mcspi
[    7.512620] [mcspi_probe] bus_num=3, pdev_name=480b8000.spi
[    7.512648] [mcspi_probe] MCSPI3 controller's attributes: @phys=0x480b8000, @virt=0xfa0b8000
[    7.512700] [mcspi_slave_setup] perform a soft reset of the MCSPI controller...
[    7.512713] [mcspi_check_clock_domains] clock domains are OK
[    7.516189] [mcspi_test_rx_lines] CS0 input signal line toggles well
[    7.520085] [mcspi_test_rx_lines] SCLK input signal line toggles well
[    7.520095] [mcspi_test_rx_lines] D1 input signal line toggles well
[    7.520246] mcspi_slave_rx 480b8000.spi: registered slave rx spi_slave_rx3
[    7.525537] [AAAAAAAAAA_init]: AAAAAAAAAA driver successfully registered
[    7.525566] bus for spi_slave_rx is spi_slave_rx3.0
[    7.525739] spi_slave_rx spi_slave_rx3.0: setup mode 0, 16 bits/w, 30000000 Hz max --> 1
[    7.526079] AAAAAAAAAA spi_slave_rx3.0: driver probed
[    7.526335] AAAAAAAAAA AAAAAAAAAA0: new device created
[    7.526389] mcspi_slave_rx 480b8000.spi: registered child spi_slave_rx3.0
[    8.582895] omap-rproc 40800000.dsp: assigned reserved memory node dsp1_cma@99000000
[    8.582985]  remoteproc0: 40800000.dsp is available
[    8.582998]  remoteproc0: Note: remoteproc is still under development and considered experimental.
[    8.583010]  remoteproc0: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
[    8.652389] omap-mailbox 48840000.mailbox: omap mailbox rev 0x400
[    8.709729] m25p80 spi32766.0: found n25q512ax3, expected n25q512a
[    8.709792] m25p80 spi32766.0: n25q512ax3 (65536 Kbytes)
[    8.709928] 9 ofpart partitions found on MTD device spi32766.0
[    8.709940] Creating 9 MTD partitions on "spi32766.0":
[    8.709955] 0x000000000000-0x000000020000 : "mtd_BBBBBBBBBB_mlo"
[    8.731344] 0x000000020000-0x0000000f0000 : "mtd_BBBBBBBBBB_uboot"
[    8.753194] 0x0000000f0000-0x000000100000 : "mtd_BBBBBBBBBB_env"
[    8.793082] 0x000000100000-0x000000bc0000 : "mtd_BBBBBBBBBB_zimage"
[    8.816730] 0x000000bc0000-0x000000c00000 : "mtd_BBBBBBBBBB_dtb"
[    8.851253] 0x000000c00000-0x000001400000 : "mtd_aml"
[    8.886014] 0x000001400000-0x000002bc0000 : "mtd_CCCCCCCCCC_zimage"
[    8.902999] 0x000002bc0000-0x000002c00000 : "mtd_CCCCCCCCCC_dtb"
[    8.927390] 0x000002c00000-0x000004000000 : "mtd_loads"
[    8.993868] omap_rng 48090000.rng: OMAP Random Number Generator ver. 20
[    9.115393] libata version 3.00 loaded.
[    9.143241] ahci 4a140000.sata: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x0 impl platform mode
[    9.143265] ahci 4a140000.sata: flags: 64bit ncq sntf pm led clo only pmp pio slum part ccc apst 
[    9.198528] scsi host0: ahci
[    9.199174] ata1: DUMMY
[    9.255278]  remoteproc0: registered virtio0 (type 7)
[    9.280497]  remoteproc0: powering up 40800000.dsp
[    9.370237]  remoteproc0: Booting fw image dra7-dsp1-fw.xe66, size 22296088
[    9.377758] omap_hwmod: mmu0_dsp1: _wait_target_disable failed
[    9.377815] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0
[    9.377939] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0
[    9.384093] net eth0: initializing cpsw version 1.15 (0)
[    9.384135] net eth0: initialized cpsw ale version 1.4
[    9.384148] net eth0: ALE Table size 1024
[    9.411850]  remoteproc0: remote processor 40800000.dsp is now up
[    9.421186] virtio_rpmsg_bus virtio0: rpmsg host is online
[    9.421282] virtio_rpmsg_bus virtio0: creating channel rpmsg-proto addr 0x3d
[    9.445918] NET: Registered protocol family 41
[    9.461974] net eth0: phy found : id is : 0x0
[    9.462152] cpsw-phy-sel 4a002554.cpsw-phy-sel: RMII External clock is not supported
[    9.512862] net eth1: initializing cpsw version 1.15 (0)
[    9.592087] net eth1: phy found : id is : 0x0
[    9.592254] cpsw-phy-sel 4a002554.cpsw-phy-sel: RMII External clock is not supported
[    9.790859] nand: nand_decode_bbm_options: mtd->writesize=8192
[    9.790877] nand: nand_decode_bbm_options: chip->options=0x00010200
[    9.790889] nand: nand_decode_bbm_options: chip->badblockpos=NAND_LARGE_BADBLOCK_POS
[    9.790900] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x68
[    9.790910] nand: Micron MT29F32G08ABAAAWP
[    9.790922] nand: 4096 MiB, SLC, erase size: 1024 KiB, page size: 8192, OOB size: 448
[    9.790938] omap2-nand 8000000.nand: xfer_type=0
[    9.791040] omap2-nand 8000000.nand: ecc_opt=6
[    9.791049] using OMAP_ECC_BCH16_CODE_HW ECC scheme
[    9.791103] 1 ofpart partitions found on MTD device 8000000.nand
[    9.791114] Creating 1 MTD partitions on "8000000.nand":
[    9.791128] 0x000000000000-0x000100000000 : "mtd_nand"
[   10.721213] ubi0: attaching mtd9
[   11.462108] cpsw 48484000.ethernet eth0: Link is Up - 10Mbps/Full - flow control off
[   11.591986] cpsw 48484000.ethernet eth1: Link is Up - 100Mbps/Full - flow control off
[   18.995122] ubi0: scanning is finished
[   19.010621] ubi0: attached mtd9 (name "mtd_nand", size 4096 MiB)
[   19.010640] ubi0: PEB size: 1048576 bytes (1024 KiB), LEB size: 1032192 bytes
[   19.010653] ubi0: min./max. I/O unit sizes: 8192/8192, sub-page size 8192
[   19.010665] ubi0: VID header offset: 8192 (aligned 8192), data offset: 16384
[   19.010675] ubi0: good PEBs: 4094, bad PEBs: 2, corrupted PEBs: 0
[   19.010686] ubi0: user volume: 2, internal volumes: 1, max. volumes count: 128
[   19.010698] ubi0: max/mean erase counter: 13/6, WL threshold: 4096, image sequence number: 968885737
[   19.010708] ubi0: available PEBs: 0, total reserved PEBs: 4094, PEBs reserved for bad PEB handling: 78
[   19.012727] ubi0: background thread "ubi_bgt0d" started, PID 395
[   19.062232] UBIFS (ubi0:0): background thread "ubifs_bgt0_0" started, PID 401
[   19.311096] UBIFS (ubi0:0): recovery needed
[   19.810257] UBIFS (ubi0:0): recovery completed
[   19.810283] UBIFS (ubi0:0): UBIFS: mounted UBI device 0, volume 0, name "log"
[   19.810297] UBIFS (ubi0:0): LEB size: 1032192 bytes (1008 KiB), min./max. I/O unit sizes: 8192 bytes/8192 bytes
[   19.810312] UBIFS (ubi0:0): FS size: 94961664 bytes (90 MiB, 92 LEBs), journal size 8257537 bytes (7 MiB, 6 LEBs)
[   19.810325] UBIFS (ubi0:0): reserved for root: 4485273 bytes (4380 KiB)
[   19.810341] UBIFS (ubi0:0): media format: w4/r0 (latest is w4/r0), UUID B6FF7C0E-09C6-4157-880B-4F86E5FA08F6, small LPT model
[   19.842217] UBIFS (ubi0:1): background thread "ubifs_bgt0_1" started, PID 405
[   20.089779] omap_hwmod: mmu1_dsp1: _wait_target_disable failed
[   20.097195] omap_hwmod: mmu0_dsp1: _wait_target_disable failed
[   20.105398] UBIFS (ubi0:1): recovery needed
[   20.600194] UBIFS (ubi0:1): recovery completed
[   20.600219] UBIFS (ubi0:1): UBIFS: mounted UBI device 0, volume 1, name "KKKKKKKKKK"
[   20.600234] UBIFS (ubi0:1): LEB size: 1032192 bytes (1008 KiB), min./max. I/O unit sizes: 8192 bytes/8192 bytes
[   20.600249] UBIFS (ubi0:1): FS size: 4025548800 bytes (3839 MiB, 3900 LEBs), journal size 33030144 bytes (31 MiB, 32 LEBs)
[   20.600261] UBIFS (ubi0:1): reserved for root: 4952683 bytes (4836 KiB)
[   20.600277] UBIFS (ubi0:1): media format: w4/r0 (latest is w4/r0), UUID D20EB50E-1728-453C-8EA3-CC4B0CE812F8, small LPT model
[   20.923332] AAAAAAAAAA spi_slave_rx3.0: Starting reception
[   21.591063] random: nonblocking pool is initialized
[  201.291338] omap_hwmod: mmu0_dsp1: _wait_target_disable failed
[  201.291401] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0
[  201.297827] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0
[  213.049817] omap_hwmod: mmu1_dsp1: _wait_target_disable failed
[  213.057881] omap_hwmod: mmu0_dsp1: _wait_target_disable failed
[  420.492628] edma 43300000.edma: dma_ccerr_handler: Error interrupt without error event!
[  420.810455] edma 43300000.edma: dma_ccerr_handler: Error interrupt without error event!
[  420.870542] edma 43300000.edma: dma_ccerr_handler: Error interrupt without error event!
[  432.694061] omap_hwmod: mmu0_dsp1: _wait_target_disable failed
[  432.694125] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0
[  432.696089] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0
[  443.059609] omap_hwmod: mmu1_dsp1: _wait_target_disable failed
[  443.073058] omap_hwmod: mmu0_dsp1: _wait_target_disable failed

). I observe any significant changes in the log message. Can you explain why it [IRQ_NONE to IRQ_HANDLED] could impact the configuration?

In my system, I have 2 UARTs connected to the board. The eDMA problem happens, when I use OpenCL [which freezes the first UART] and simultaneously I send a transmission frame across the second UART.

With Ftrace `echo "edma_* *omap_8250*" > set_ftrace_filter`, when I run OpenCL in a SSH (`while (true) do echo "offline: start" > /home/root/tracing/trace_marker; ./offline ; echo "offline: stop" > /home/root/tracing/trace_marker done;`) and simultaneously I send a transmission frame across the second UART, I obtain the eDMA error in the kernel log, and the following Ftrace logs :

Fullscreen edma-omap-dma-16h32-08-11-2017_for_TI.log Download

# tracer: function
#
# entries-in-buffer/entries-written: 113/113   #P:1
#
#                              _-----=> irqs-off
#                             / _----=> need-resched
#                            |/  _-----=> need-resched_lazy
#                            || / _---=> hardirq/softirq
#                            ||| / _--=> preempt-depth
#                            |||| / _-=> preempt-lazy-depth
#                            ||||| / _-=> migrate-disable   
#                            |||||| /    delay
#           TASK-PID   CPU#  |||||||   TIMESTAMP  FUNCTION
#              | |       |   |||||||      |         |
       CCCCCCCCC-809   [000] d..h2..   293.510611: omap_8250_rx_dma <-omap8250_irq                  <-- arrivée d'une interruption
       CCCCCCCCC-809   [000] d..h2..   293.510618: omap_8250_rx_dma_flush <-omap_8250_rx_dma        <-- initialisation d'un transfert DMA
       CCCCCCCCC-809   [000] d..h3..   293.510622: edma_tx_status <-omap_8250_rx_dma_flush
       CCCCCCCCC-809   [000] d..h3..   293.510626: edma_dma_pause <-omap_8250_rx_dma_flush
       CCCCCCCCC-809   [000] d..h3..   293.510631: edma_tx_status <-__dma_rx_do_complete
       CCCCCCCCC-809   [000] d..h3..   293.510634: edma_terminate_all <-__dma_rx_do_complete
       CCCCCCCCC-809   [000] d..h4..   293.510636: edma_stop <-edma_terminate_all
       CCCCCCCCC-809   [000] d..h2..   293.510731: omap_8250_rx_dma <-omap8250_irq
       CCCCCCCCC-809   [000] d..h3..   293.510734: edma_prep_slave_sg <-omap_8250_rx_dma
       CCCCCCCCC-809   [000] d..h3..   293.510739: edma_config_pset <-edma_prep_slave_sg
       CCCCCCCCC-809   [000] d..h3..   293.510744: edma_issue_pending <-omap_8250_rx_dma
       CCCCCCCCC-809   [000] d..h4..   293.510747: edma_execute <-edma_issue_pending
       CCCCCCCCC-809   [000] d..h4..   293.510750: edma_link <-edma_execute
       CCCCCCCCC-809   [000] d..h4..   293.510752: edma_start <-edma_execute
       CCCCCCCCC-428   [000] d..h2..   293.510889: omap_8250_rx_dma <-omap8250_irq
       CCCCCCCCC-428   [000] d..h2..   293.510892: omap_8250_rx_dma_flush <-omap_8250_rx_dma
       CCCCCCCCC-428   [000] d..h3..   293.510894: edma_tx_status <-omap_8250_rx_dma_flush
       CCCCCCCCC-428   [000] d..h3..   293.510897: edma_dma_pause <-omap_8250_rx_dma_flush
       CCCCCCCCC-428   [000] d..h3..   293.510900: edma_tx_status <-__dma_rx_do_complete
       CCCCCCCCC-428   [000] d..h3..   293.510902: edma_terminate_all <-__dma_rx_do_complete
       CCCCCCCCC-428   [000] d..h4..   293.510904: edma_stop <-edma_terminate_all
       CCCCCCCCC-428   [000] d..h2..   293.510972: omap_8250_rx_dma <-omap8250_irq
       CCCCCCCCC-428   [000] d..h3..   293.510975: edma_prep_slave_sg <-omap_8250_rx_dma
       CCCCCCCCC-428   [000] d..h3..   293.510978: edma_config_pset <-edma_prep_slave_sg
       CCCCCCCCC-428   [000] d..h3..   293.510982: edma_issue_pending <-omap_8250_rx_dma
       CCCCCCCCC-428   [000] d..h4..   293.510983: edma_execute <-edma_issue_pending
       CCCCCCCCC-428   [000] d..h4..   293.510986: edma_link <-edma_execute
       CCCCCCCCC-428   [000] d..h4..   293.510988: edma_start <-edma_execute
       CCCCCCCCC-428   [000] d..h2..   293.511130: omap_8250_rx_dma <-omap8250_irq
       CCCCCCCCC-428   [000] d..h2..   293.511133: omap_8250_rx_dma_flush <-omap_8250_rx_dma
       CCCCCCCCC-428   [000] d..h3..   293.511135: edma_tx_status <-omap_8250_rx_dma_flush
       CCCCCCCCC-428   [000] d..h3..   293.511512: edma_dma_pause <-omap_8250_rx_dma_flush
       CCCCCCCCC-428   [000] d..h3..   293.511516: edma_tx_status <-__dma_rx_do_complete
       CCCCCCCCC-428   [000] d..h3..   293.511893: edma_terminate_all <-__dma_rx_do_complete
       CCCCCCCCC-428   [000] d..h4..   293.511895: edma_stop <-edma_terminate_all
       CCCCCCCCC-428   [000] d..h2..   293.511952: omap_8250_rx_dma <-omap8250_irq
       CCCCCCCCC-428   [000] d..h3..   293.511955: edma_prep_slave_sg <-omap_8250_rx_dma
       CCCCCCCCC-428   [000] d..h3..   293.511957: edma_config_pset <-edma_prep_slave_sg
       CCCCCCCCC-428   [000] d..h3..   293.511962: edma_issue_pending <-omap_8250_rx_dma
       CCCCCCCCC-428   [000] d..h4..   293.511963: edma_execute <-edma_issue_pending
       CCCCCCCCC-428   [000] d..h4..   293.511965: edma_link <-edma_execute
       CCCCCCCCC-428   [000] d..h4..   293.511967: edma_start <-edma_execute
        dropbear-781   [000] d..h2..   293.600629: omap_8250_rx_dma <-omap8250_irq
        dropbear-781   [000] d..h2..   293.600636: omap_8250_rx_dma_flush <-omap_8250_rx_dma
        dropbear-781   [000] d..h3..   293.600639: edma_tx_status <-omap_8250_rx_dma_flush
        dropbear-781   [000] d..h3..   293.601018: edma_dma_pause <-omap_8250_rx_dma_flush
        dropbear-781   [000] d..h3..   293.601022: edma_tx_status <-__dma_rx_do_complete
        dropbear-781   [000] d..h3..   293.601399: edma_terminate_all <-__dma_rx_do_complete
        dropbear-781   [000] d..h4..   293.601402: edma_stop <-edma_terminate_all
        dropbear-781   [000] dn.h2..   293.601474: omap_8250_rx_dma <-omap8250_irq
        dropbear-781   [000] dn.h3..   293.601477: edma_prep_slave_sg <-omap_8250_rx_dma
        dropbear-781   [000] dn.h3..   293.601483: edma_config_pset <-edma_prep_slave_sg
        dropbear-781   [000] dn.h3..   293.601489: edma_issue_pending <-omap_8250_rx_dma
        dropbear-781   [000] dn.h4..   293.601491: edma_execute <-edma_issue_pending
        dropbear-781   [000] dn.h4..   293.601494: edma_link <-edma_execute
        dropbear-781   [000] dn.h4..   293.601497: edma_start <-edma_execute
          <idle>-0     [000] d..h3..   293.705653: omap_8250_rx_dma <-omap8250_irq
          <idle>-0     [000] d..h3..   293.705659: omap_8250_rx_dma_flush <-omap_8250_rx_dma
          <idle>-0     [000] d..h4..   293.705662: edma_tx_status <-omap_8250_rx_dma_flush
          <idle>-0     [000] d..h4..   293.706041: edma_dma_pause <-omap_8250_rx_dma_flush
          <idle>-0     [000] d..h4..   293.706045: edma_tx_status <-__dma_rx_do_complete
          <idle>-0     [000] d..h4..   293.706423: edma_terminate_all <-__dma_rx_do_complete
          <idle>-0     [000] d..h5..   293.706425: edma_stop <-edma_terminate_all
          <idle>-0     [000] dn.h3..   293.706497: omap_8250_rx_dma <-omap8250_irq
          <idle>-0     [000] dn.h4..   293.706500: edma_prep_slave_sg <-omap_8250_rx_dma
          <idle>-0     [000] dn.h4..   293.706505: edma_config_pset <-edma_prep_slave_sg
          <idle>-0     [000] dn.h4..   293.706511: edma_issue_pending <-omap_8250_rx_dma
          <idle>-0     [000] dn.h5..   293.706513: edma_execute <-edma_issue_pending
          <idle>-0     [000] dn.h5..   293.706517: edma_link <-edma_execute
          <idle>-0     [000] dn.h5..   293.706522: edma_start <-edma_execute
       CCCCCCCCC-424   [000] ....1..   293.706932: omap_8250_shutdown <-serial8250_shutdown     <-- serial8250_shutdown: désactivation du port série ??
       CCCCCCCCC-424   [000] ....1..   293.706938: omap_8250_rx_dma <-omap_8250_shutdown
       CCCCCCCCC-424   [000] ....1..   293.706940: omap_8250_rx_dma_flush <-omap_8250_rx_dma
       CCCCCCCCC-424   [000] d...2..   293.706943: edma_tx_status <-omap_8250_rx_dma_flush
       CCCCCCCCC-424   [000] d...2..   293.706946: edma_dma_pause <-omap_8250_rx_dma_flush
       CCCCCCCCC-424   [000] d...2..   293.706950: edma_tx_status <-__dma_rx_do_complete
       CCCCCCCCC-424   [000] d...2..   293.706952: edma_terminate_all <-__dma_rx_do_complete
       CCCCCCCCC-424   [000] d...3..   293.706954: edma_stop <-edma_terminate_all
       CCCCCCCCC-424   [000] ....1..   293.706971: edma_terminate_all <-serial8250_release_dma
       CCCCCCCCC-424   [000] ....1..   293.706986: edma_synchronize <-dma_chan_put
       CCCCCCCCC-424   [000] ....1..   293.706989: edma_free_chan_resources <-dma_chan_put
       CCCCCCCCC-424   [000] ....1..   293.706991: edma_stop <-edma_free_chan_resources
       CCCCCCCCC-424   [000] ....1..   293.706995: edma_free_slot <-edma_free_chan_resources
       CCCCCCCCC-424   [000] ....1..   293.706997: edma_free_channel <-edma_free_chan_resources
       CCCCCCCCC-424   [000] ....1..   293.706999: edma_stop <-edma_free_channel
       CCCCCCCCC-424   [000] ....1..   293.707005: edma_terminate_all <-serial8250_release_dma
       CCCCCCCCC-424   [000] ....1..   293.707009: edma_synchronize <-dma_chan_put
       CCCCCCCCC-424   [000] ....1..   293.707011: edma_free_chan_resources <-dma_chan_put
       CCCCCCCCC-424   [000] ....1..   293.707013: edma_stop <-edma_free_chan_resources
       CCCCCCCCC-424   [000] ....1..   293.707015: edma_free_slot <-edma_free_chan_resources
       CCCCCCCCC-424   [000] ....1..   293.707017: edma_free_channel <-edma_free_chan_resources
       CCCCCCCCC-424   [000] ....1..   293.707018: edma_stop <-edma_free_channel
       CCCCCCCCC-424   [000] ....1..   293.707050: omap_8250_pm <-serial8250_pm                  <-- serial8250_pm: intervention du Power Management
       CCCCCCCCC-424   [000] ....1..   293.707326: omap_8250_pm <-serial8250_pm
       CCCCCCCCC-424   [000] ....1..   293.707338: omap_8250_startup <-serial8250_startup        <-- serial8250_startup: résactivation du port série ??
       CCCCCCCCC-424   [000] ....1..   293.707475: edma_alloc_chan_resources <-dma_chan_get
       CCCCCCCCC-424   [000] ....1..   293.707477: edma_stop <-edma_alloc_chan_resources
       CCCCCCCCC-424   [000] ....1..   293.707480: edma_assign_channel_eventq <-edma_alloc_chan_resources
       CCCCCCCCC-424   [000] ....1..   293.707482: edma_alloc_slot <-edma_alloc_chan_resources
       CCCCCCCCC-424   [000] ....1..   293.707485: edma_slave_config <-serial8250_request_dma
       CCCCCCCCC-424   [000] ....1..   293.707537: edma_alloc_chan_resources <-dma_chan_get
       CCCCCCCCC-424   [000] ....1..   293.707538: edma_stop <-edma_alloc_chan_resources
       CCCCCCCCC-424   [000] ....1..   293.707540: edma_assign_channel_eventq <-edma_alloc_chan_resources
       CCCCCCCCC-424   [000] ....1..   293.707542: edma_alloc_slot <-edma_alloc_chan_resources
       CCCCCCCCC-424   [000] ....1..   293.707545: edma_slave_config <-serial8250_request_dma
       CCCCCCCCC-424   [000] ....1..   293.707655: omap_8250_rx_dma <-omap_8250_startup
       CCCCCCCCC-424   [000] d...2..   293.707658: edma_prep_slave_sg <-omap_8250_rx_dma
       CCCCCCCCC-424   [000] d...2..   293.707661: edma_config_pset <-edma_prep_slave_sg
       CCCCCCCCC-424   [000] d...2..   293.707666: edma_issue_pending <-omap_8250_rx_dma
       CCCCCCCCC-424   [000] d...3..   293.707668: edma_execute <-edma_issue_pending
       CCCCCCCCC-424   [000] d...3..   293.707670: edma_link <-edma_execute
       CCCCCCCCC-424   [000] d...3..   293.707672: edma_start <-edma_execute
       CCCCCCCCC-424   [000] ....1..   293.707676: omap_8250_set_termios <-serial8250_set_termios <-- serial8250_set_termios: configuration du port

I have seen the following patches from the mainline kernel which could be impacting my configuration:

* serial: 8250: 8250_omap: Fix race b/w dma completion and RX timeout (a1bfb6eb300d008decfbcdf13b0fda536d22dea9)

* serial: 8250: omap: Disable DMA for console UART (84b40e3b57eef1417479c00490dd4c9f6e5ffdbc)

What do you think about these patches? I consider applying them to see soon, if one of them could solve the eDMA problem.

Have you others suggestions?

0 Yordan Kovachev over 7 years ago in reply to Darth Vader

TI__Guru**** 161600 points

Hi,

Both patches:
patchwork.kernel.org/.../
patchwork.kernel.org/.../
are already applied in the latest TI Linux SDK (v04.01.00.06, using kernel version 4.9.41).

Can you share which SDK version are you using? If it is an older one, then yes, those patches are a good idea to try and see if they'll fix your issue.

Best Regards,
Yordan

0 Darth Vader over 7 years ago in reply to Yordan Kovachev

Prodigy 50 points

Hi,

My SDK version is ti-processor-sdk-linux-rt-am57xx-evm-03.02.00.05-Linux-x86

I tried these patches, they don't solve my problem

Disable the dma, avoid the UART console freezing, but the eDMA problem is still present

0 Yordan Kovachev over 7 years ago in reply to Darth Vader

TI__Guru**** 161600 points

Hi,

Just wanted to let you know that I am looking into this.

Best Regards,
Yordan

0 Yordan Kovachev over 7 years ago in reply to Yordan Kovachev

TI__Guru**** 161600 points

Hi,

Can you share your dts node for the uarts? Are you certain that you're not using the same dma channel in more than one SoC module?

Best Regards,
Yordan

0 Romain Naour over 7 years ago in reply to Yordan Kovachev

Intellectual 516 points

Hi Yordan,

I'm working with "Darth Vader" this issue.

Here is the custom.dts file

Fullscreen custom-board-for-ti.dts.txt Download

/*
 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
    model = "TI AM5718 CUSTOM BOARD";
    compatible = "ti,am5718", "ti,dra722", "ti,dra72", "ti,dra7";

    memory@80000000 {
        device_type = "memory";
        reg = <0x0 0x80000000 0x0 0x20000000>;
    };

    reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		dsp1_cma_pool: dsp1_cma@99000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x99000000 0x0 0x4000000>;
			reusable;
			status = "okay";
		};

                cmem_block_mem_0: cmem_block_mem@90000000 {
                        reg = <0x0 0x90000000 0x0 0x05800000>;
                        no-map;
                        status = "okay";
                };
    };

        cmem {
                compatible = "ti,cmem";
                #address-cells = <1>;
                #size-cells = <0>;

		#pool-size-cells = <2>;

                status = "okay";

                cmem_block_0: cmem_block@0 {
                        reg = <0>;
                        memory-region = <&cmem_block_mem_0>;
                        cmem-buf-pools = <1 0x0 0x05800000>;
                };
        };
};

&dra7_pmx_core {
    i2c1_pins_default: i2c1_pins_default {
        pinctrl-single,pins = <
            0x404 (PIN_INPUT | PULL_DIS | MUX_MODE0)    /* I2C1 - i2c1_scl on C20 - I2C_GPC_PMIC */
            0x400 (PIN_INPUT | PULL_DIS | MUX_MODE0)    /* I2C1 - i2c1_sda on C21 - I2C_GPC_PMIC */
        >;
    };

    i2c2_pins_default: i2c2_pins_default {
        pinctrl-single,pins = <
            0x40C (PIN_INPUT | PULL_DIS | MUX_MODE0)    /* I2C2 - i2c2_scl on F17 - I2C2_AVS_PMIC */
            0x408 (PIN_INPUT | PULL_DIS | MUX_MODE0)    /* I2C2 - i2c2_sda on C25 - I2C2_AVS_PMIC */
        >;
    };

    uart1_pins_default: uart1_pins_default {
        pinctrl-single,pins = <
            0x3E0 (PIN_INPUT | PULL_DIS | MUX_MODE0)    /* UART1 - uart1_rxd on B27 - UART1 (UART1_RXD) */
            0x3E4 (PIN_OUTPUT | PULL_DIS | MUX_MODE0)   /* UART1 - uart1_txd on C26 - UART1 (UART1_TXD) */
        >;
    };

    uart3_pins_default: uart3_pins_default {
        pinctrl-single,pins = <
            0x3F8 (PIN_INPUT | PULL_DIS | MUX_MODE2)    /* UART3 - uart3_rxd on D27 - UART3 (UART2_CTSN) */
            0x3FC (PIN_OUTPUT | PULL_DIS | MUX_MODE1)   /* UART3 - uart3_txd on C28 - UART3 (UART2_RTSN) */
        >;
    };

    pruss1_uart_pins_default: pruss1_uart_pins_default {
        pinctrl-single,pins = <
        0x168 (PIN_INPUT | PULL_DIS | MUX_MODE11)       /* PRUSS1_UART - pr1_uart0_rxd on F2 - PRU_UART3 */
        0x16C (PIN_OUTPUT | PULL_DIS | MUX_MODE11)      /* PRUSS1_UART - pr1_uart0_txd on F3 - PRU_UART3 */
        >;
    };

    spi_pins_default: spi_pins_default {
        pinctrl-single,pins = <
            0x394 (PIN_OUTPUT | PULL_DIS | MUX_MODE1)   /* SPI4 - spi4_sclk on AC8 - TECU */
            0x39C (PIN_OUTPUT | PULL_DIS | MUX_MODE1)   /* SPI4 - spi4_d0 on AB8 - TECU */
            0x398 (PIN_INPUT | PULL_DIS | MUX_MODE1)    /* SPI4 - spi4_d1 on AD6 - TECU */
            0x3A0 (PIN_OUTPUT | PULL_DIS | MUX_MODE1)   /* SPI4 - spi4_cs0 on AB5 - TECU */
            0x3A4 (PIN_INPUT | PULL_DIS | MUX_MODE0)    /* SPI1 - spi1_sclk on A25 - LO_SPI_ADC */
            0x3B0 (PIN_INPUT | PULL_DIS | MUX_MODE0)    /* SPI1 - spi1_cs0 on A24 - LO_SPI_ADC */
            0x3AC (PIN_INPUT | PULL_DIS | MUX_MODE0)    /* SPI1 - spi1_d0 on B25 - LO_SPI_ADC */
        >;
    };

    mcspi3_pins: mcspi3_pins {
        pinctrl-single,pins = <
            0x380 (PIN_INPUT | PULL_DIS | MUX_MODE1)   	/* SPI3 - spi3_sclk on AC4 - DIVIO AVM */
            0x388 (PIN_OUTPUT | PULL_DIS | MUX_MODE1)   /* SPI3 - spi3_d0 on AC6 - DIVIO AVM */
            0x384 (PIN_INPUT | PULL_DIS | MUX_MODE1)    /* SPI3 - spi3_d1 on AC7 - DIVIO AVM */
            0x38C (PIN_INPUT | PULL_DIS | MUX_MODE1)   	/* SPI3 - spi3_cs0 on AC9 - DIVIO AVM */
        >;
    };

    gpio_pins_default: gpio_pins_default {
        pinctrl-single,pins = <
            0x158 (PIN_INPUT | PULL_DIS | MUX_MODE14)   /* GPIO3 - gpio3_29 on G2 - GPIO3 */
            0x164 (PIN_INPUT | PULL_DIS | MUX_MODE14)   /* GPIO4 - gpio4_0 on G6 - GPIO4 */
            0x170 (PIN_INPUT | PULL_DIS | MUX_MODE14)   /* GPIO4 - gpio4_3 on D1 - GPIO4 */
            0x174 (PIN_INPUT | PULL_DIS | MUX_MODE14)   /* GPIO4 - gpio4_4 on E2 - GPIO4 */
            0x178 (PIN_INPUT | PULL_DIS | MUX_MODE14)   /* GPIO4 - gpio4_5 on D2 - GPIO4 */
            0x17C (PIN_INPUT | PULL_DIS | MUX_MODE14)   /* GPIO4 - gpio4_6 on F4 - GPIO4 */
            0x184 (PIN_INPUT | PULL_DIS | MUX_MODE14)   /* GPIO4 - gpio4_8 on E4 - GPIO4 */
            0x190 (PIN_INPUT | PULL_DIS | MUX_MODE14)   /* GPIO4 - gpio4_11 on D3 - GPIO4 */
            0x198 (PIN_INPUT | PULL_DIS | MUX_MODE14)   /* GPIO4 - gpio4_13 on D5 - GPIO4 */
            0x19C (PIN_INPUT | PULL_DIS | MUX_MODE14)   /* GPIO4 - gpio4_14 on C2 - GPIO4 */
            0x1A0 (PIN_INPUT | PULL_DIS | MUX_MODE14)   /* GPIO4 - gpio4_15 on C3 - GPIO4 */
            0x1AC (PIN_INPUT | PULL_DIS | MUX_MODE14)   /* GPIO4 - gpio4_25 on D6 - GPIO4 */
            0x1B0 (PIN_INPUT | PULL_DIS | MUX_MODE14)   /* GPIO4 - gpio4_26 on C5 - GPIO4 */
            0x1B4 (PIN_INPUT | PULL_DIS | MUX_MODE14)   /* GPIO4 - gpio4_27 on A3 - GPIO4 */
        >;
    };

    gpio_pins_virtual: gpio_pins_virtual {
        pinctrl-single,pins = <
            0x154 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE11 | MUX_MODE14)  /* GPIO3 - gpio3_28 on E1 - GPIO3 */
            0x15C (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE11 | MUX_MODE14)  /* GPIO3 - gpio3_30 on H7 - GPIO3 */
            0x160 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE9 | MUX_MODE14)   /* GPIO3 - gpio3_31 on G1 - GPIO3 */
            0x188 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE9 | MUX_MODE14)   /* GPIO4 - gpio4_9 on F5 - GPIO4 */
            0x194 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE9 | MUX_MODE14)   /* GPIO4 - gpio4_12 on F6 - GPIO4 */
        >;
    };

    int_pins_default: int_pins_default {
        pinctrl-single,pins = <
            0x424 (PIN_INPUT | PULL_DIS | MUX_MODE1)    /* INTC - sys_nirq1 on AC16 - INT */
            0x418 (PIN_INPUT | PULL_DIS | MUX_MODE14)   /* INTC - sys_nirq2 on AD17 - INT */
        >;
    };

    mdio_pins_default: mdio_pins_default {
        pinctrl-single,pins = <
            0x3B8 (PIN_OUTPUT | PULL_DIS | MUX_MODE5)   /* MDIO - mdio_mclk on B21 - MDIO_PHY */
            0x3BC (PIN_INPUT | PULL_DIS | MUX_MODE5)    /* MDIO - mdio_d on B20 - MDIO_PHY */
        >;
    };

    gpmc_pins_default: gpmc_pins_default {
        pinctrl-single,pins = <
            0x1C (PIN_INPUT | PULL_DIS | MUX_MODE0)     /* GPMC - gpmc_ad7 on L2 - NAND */
            0x18 (PIN_INPUT | PULL_DIS | MUX_MODE0)     /* GPMC - gpmc_ad6 on L3 - NAND */
            0x14 (PIN_INPUT | PULL_DIS | MUX_MODE0)     /* GPMC - gpmc_ad5 on L4 - NAND */
            0x10 (PIN_INPUT | PULL_DIS | MUX_MODE0)     /* GPMC - gpmc_ad4 on L6 - NAND */
            0xC (PIN_INPUT | PULL_DIS | MUX_MODE0)      /* GPMC - gpmc_ad3 on M1 - NAND */
            0x8 (PIN_INPUT | PULL_DIS | MUX_MODE0)      /* GPMC - gpmc_ad2 on L5 - NAND */
            0x4 (PIN_INPUT | PULL_DIS | MUX_MODE0)      /* GPMC - gpmc_ad1 on M2 - NAND */
            0x0 (PIN_INPUT | PULL_DIS | MUX_MODE0)      /* GPMC - gpmc_ad0 on M6 - NAND */
            0xD8 (PIN_INPUT | PULL_DIS | MUX_MODE0)     /* GPMC - gpmc_wait0 on N2 - NAND */
            0xC0 (PIN_INPUT | PULL_DIS | MUX_MODE3)     /* GPMC - gpmc_wait1 on P7 - NAND */
            0xB4 (PIN_OUTPUT | PULL_DIS | MUX_MODE0)    /* GPMC - gpmc_cs0 on T1 - NAND */
            0xB0 (PIN_OUTPUT | PULL_DIS | MUX_MODE0)    /* GPMC - gpmc_cs1 on H6 - NAND */
            0xC4 (PIN_OUTPUT | PULL_DIS | MUX_MODE0)    /* GPMC - gpmc_advn_ale on N1 - NAND */
            0xC8 (PIN_OUTPUT | PULL_DIS | MUX_MODE0)    /* GPMC - gpmc_oen_ren on M5 - NAND */
            0xCC (PIN_OUTPUT | PULL_DIS | MUX_MODE0)    /* GPMC - gpmc_wen on M3 - NAND */
            0xD0 (PIN_OUTPUT | PULL_DIS | MUX_MODE0)    /* GPMC - gpmc_ben0 on N6 - NAND */
        >;
    };

    gpmc_pins_virtual: gpmc_pins_virtual {
        pinctrl-single,pins = <
            0x1C (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE0)    /* GPMC - gpmc_ad7 on L2 - NAND */
            0x18 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE0)    /* GPMC - gpmc_ad6 on L3 - NAND */
            0x14 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE0)    /* GPMC - gpmc_ad5 on L4 - NAND */
            0x10 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE0)    /* GPMC - gpmc_ad4 on L6 - NAND */
            0xC (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE0)     /* GPMC - gpmc_ad3 on M1 - NAND */
            0x8 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE0)     /* GPMC - gpmc_ad2 on L5 - NAND */
            0x4 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE0)     /* GPMC - gpmc_ad1 on M2 - NAND */
            0x0 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE0)     /* GPMC - gpmc_ad0 on M6 - NAND */
            0xD8 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE15 | MUX_MODE0)    /* GPMC - gpmc_wait0 on N2 - NAND */
            0xC0 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE15 | MUX_MODE3)    /* GPMC - gpmc_wait1 on P7 - NAND */
            0xB4 (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE15 | MUX_MODE0)   /* GPMC - gpmc_cs0 on T1 - NAND */
            0xB0 (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE15 | MUX_MODE0)   /* GPMC - gpmc_cs1 on H6 - NAND */
            0xC4 (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE15 | MUX_MODE0)   /* GPMC - gpmc_advn_ale on N1 - NAND */
            0xC8 (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE15 | MUX_MODE0)   /* GPMC - gpmc_oen_ren on M5 - NAND */
            0xCC (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE15 | MUX_MODE0)   /* GPMC - gpmc_wen on M3 - NAND */
            0xD0 (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE15 | MUX_MODE0)   /* GPMC - gpmc_ben0 on N6 - NAND */
        >;
    };

    qspi1_pins_default: qspi1_pins_default {
        pinctrl-single,pins = <
            0x88 (PIN_OUTPUT | PULL_DIS | MUX_MODE1)    /* QSPI1 - qspi1_sclk on R2 - NOR */
            0x74 (PIN_INPUT | PULL_DIS | MUX_MODE1)     /* QSPI1 - qspi1_rtclk on R3 - NOR */
            0xB8 (PIN_OUTPUT | PULL_DIS | MUX_MODE1)    /* QSPI1 - qspi1_cs0 on P2 - NOR */
            0xBC (PIN_OUTPUT | PULL_DIS | MUX_MODE1)    /* QSPI1 - qspi1_cs1 on P1 - NOR */
            0x80 (PIN_INPUT | PULL_DIS | MUX_MODE1)     /* QSPI1 - qspi1_d0 on U1 - NOR */
            0x84 (PIN_INPUT | PULL_DIS | MUX_MODE1)     /* QSPI1 - qspi1_d1 on P3 - NOR */
            0x7C (PIN_INPUT | PULL_DIS | MUX_MODE1)     /* QSPI1 - qspi1_d2 on U2 - NOR */
            0x78 (PIN_INPUT | PULL_DIS | MUX_MODE1)     /* QSPI1 - qspi1_d3 on T2 - NOR */
        >;
    };

    qspi1_pins_manual: qspi1_pins_manual {
        pinctrl-single,pins = <
            0x88 (PIN_OUTPUT | PULL_DIS | MUX_MODE1)    /* QSPI1 - qspi1_sclk on R2 - NOR */
            0x74 (PIN_INPUT | PULL_DIS | MUX_MODE1)     /* QSPI1 - qspi1_rtclk on R3 - NOR */
            0xB8 (PIN_OUTPUT | PULL_DIS | MUX_MODE1)    /* QSPI1 - qspi1_cs0 on P2 - NOR */
            0xBC (PIN_OUTPUT | PULL_DIS | MUX_MODE1)    /* QSPI1 - qspi1_cs1 on P1 - NOR */
            0x80 (PIN_INPUT | PULL_DIS | MUX_MODE1)     /* QSPI1 - qspi1_d0 on U1 - NOR */
            0x84 (PIN_INPUT | PULL_DIS | MUX_MODE1)     /* QSPI1 - qspi1_d1 on P3 - NOR */
            0x7C (PIN_INPUT | PULL_DIS | MUX_MODE1)     /* QSPI1 - qspi1_d2 on U2 - NOR */
            0x78 (PIN_INPUT | PULL_DIS | MUX_MODE1)     /* QSPI1 - qspi1_d3 on T2 - NOR */
        >;
    };

    qspi1_pins_virtual1: qspi1_pins_virtual1 {
        pinctrl-single,pins = <
            0x88 (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE14 | MUX_MODE1)   /* QSPI1 - qspi1_sclk on R2 - NOR */
            0x74 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE14 | MUX_MODE1)    /* QSPI1 - qspi1_rtclk on R3 - NOR */
            0xB8 (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE14 | MUX_MODE1)   /* QSPI1 - qspi1_cs0 on P2 - NOR */
            0xBC (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE1)   /* QSPI1 - qspi1_cs1 on P1 - NOR */
            0x7C (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE14 | MUX_MODE1)    /* QSPI1 - qspi1_d2 on U2 - NOR */
            0x78 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE14 | MUX_MODE1)    /* QSPI1 - qspi1_d3 on T2 - NOR */
        >;
    };

    qspi1_pins_virtual2: qspi1_pins_virtual2 {
        pinctrl-single,pins = <
            0x88 (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE1)   /* QSPI1 - qspi1_sclk on R2 - NOR */
            0x74 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE1)    /* QSPI1 - qspi1_rtclk on R3 - NOR */
            0xB8 (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE1)   /* QSPI1 - qspi1_cs0 on P2 - NOR */
            0xBC (PIN_OUTPUT | PULL_DIS | MUX_VIRTUAL_MODE12 | MUX_MODE1)   /* QSPI1 - qspi1_cs1 on P1 - NOR */
            0x7C (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE1)    /* QSPI1 - qspi1_d2 on U2 - NOR */
            0x78 (PIN_INPUT | PULL_DIS | MUX_VIRTUAL_MODE13 | MUX_MODE1)    /* QSPI1 - qspi1_d3 on T2 - NOR */
        >;
    };

    debug_pins_trace: debug_pins_trace {
        pinctrl-single,pins = <
            0x430 (PIN_INPUT | PULL_DIS | MUX_MODE0)    /* DEBUGSS - tms on F18 - TRACE PORT */
            0x434 (PIN_INPUT | PULL_DIS | MUX_MODE0)    /* DEBUGSS - tdi on D23 - TRACE PORT */
            0x438 (PIN_OUTPUT | PULL_DIS | MUX_MODE0)   /* DEBUGSS - tdo on F19 - TRACE PORT */
            0x43C (PIN_INPUT | PULL_DIS | MUX_MODE0)    /* DEBUGSS - tclk on E20 - TRACE PORT */
            0x440 (PIN_INPUT | PULL_DIS | MUX_MODE0)    /* DEBUGSS - trstn on D20 - TRACE PORT */
            0x444 (PIN_OUTPUT | PULL_DIS | MUX_MODE0)   /* DEBUGSS - rtck on E18 - TRACE PORT */
            0x448 (PIN_INPUT | PULL_DIS | MUX_MODE0)    /* DEBUGSS - emu0 on G21 - TRACE PORT */
            0x44C (PIN_INPUT | PULL_DIS | MUX_MODE0)    /* DEBUGSS - emu1 on D24 - TRACE PORT */
            0x1E4 (PIN_OUTPUT | PULL_DIS | MUX_MODE2)   /* DEBUGSS - emu2 on F10 - TRACE PORT */
            0x204 (PIN_OUTPUT | PULL_DIS | MUX_MODE2)   /* DEBUGSS - emu3 on D7 - TRACE PORT */
            0x224 (PIN_OUTPUT | PULL_DIS | MUX_MODE2)   /* DEBUGSS - emu4 on A7 - TRACE PORT */
            0x1E8 (PIN_OUTPUT | PULL_DIS | MUX_MODE2)   /* DEBUGSS - emu5 on G11 - TRACE PORT */
            0x1EC (PIN_OUTPUT | PULL_DIS | MUX_MODE2)   /* DEBUGSS - emu6 on E9 - TRACE PORT */
            0x1F0 (PIN_OUTPUT | PULL_DIS | MUX_MODE2)   /* DEBUGSS - emu7 on F9 - TRACE PORT */
            0x1F4 (PIN_OUTPUT | PULL_DIS | MUX_MODE2)   /* DEBUGSS - emu8 on F8 - TRACE PORT */
            0x1F8 (PIN_OUTPUT | PULL_DIS | MUX_MODE2)   /* DEBUGSS - emu9 on E7 - TRACE PORT */
            0x208 (PIN_OUTPUT | PULL_DIS | MUX_MODE2)   /* DEBUGSS - emu10 on D8 - TRACE PORT */
            0x20C (PIN_OUTPUT | PULL_DIS | MUX_MODE2)   /* DEBUGSS - emu11 on A5 - TRACE PORT */
            0x210 (PIN_OUTPUT | PULL_DIS | MUX_MODE2)   /* DEBUGSS - emu12 on C6 - TRACE PORT */
            0x214 (PIN_OUTPUT | PULL_DIS | MUX_MODE2)   /* DEBUGSS - emu13 on C8 - TRACE PORT */
            0x218 (PIN_OUTPUT | PULL_DIS | MUX_MODE2)   /* DEBUGSS - emu14 on C7 - TRACE PORT */
            0x228 (PIN_OUTPUT | PULL_DIS | MUX_MODE2)   /* DEBUGSS - emu15 on A8 - TRACE PORT */
            0x22C (PIN_OUTPUT | PULL_DIS | MUX_MODE2)   /* DEBUGSS - emu16 on C9 - TRACE PORT */
            0x230 (PIN_OUTPUT | PULL_DIS | MUX_MODE2)   /* DEBUGSS - emu17 on A9 - TRACE PORT */
        >;
    };
};

&elm {
	status = "okay";
};

&mac {
	status = "okay";
	dual_emac;
};

&cpsw_emac0 {
	phy-mode = "rmii";
	dual_emac_res_vlan = <1>;
	fixed-link {
        speed = <10>;
        full-duplex;
    };
};

&cpsw_emac1 {
	phy-mode = "rmii";
	dual_emac_res_vlan = <2>;
	fixed-link {
        speed = <100>;
        full-duplex;
    };
};

&phy_sel {
	rmii-clock-ext;
};

&gpmc {
	status = "okay";
	ranges = <0 0 0x08000000 0x01000000>;	/* minimum GPMC partition = 16MB */
	pinctrl-names = "default";
	pinctrl-0 = <&gpmc_pins_default>;

	nand@0,0 {
		compatible = "ti,omap2-nand";
		reg = <0 0 4>;		/* device IO registers */
		ready-gpio = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
		ti,nand-ecc-opt = "bch16";
		ti,elm-id = <&elm>;
		nand-bus-width = <8>;
		gpmc,device-width = <1>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <100>;
		gpmc,cs-wr-off-ns = <100>;
		gpmc,adv-on-ns = <0>;
		gpmc,adv-rd-off-ns = <100>;
		gpmc,adv-wr-off-ns = <100>;
		gpmc,we-on-ns = <10>;
		gpmc,we-off-ns = <60>;
		gpmc,oe-on-ns = <4>;
		gpmc,oe-off-ns = <60>;
		gpmc,access-ns = <50>;
		gpmc,wr-access-ns = <80>;
		gpmc,rd-cycle-ns = <100>;
		gpmc,wr-cycle-ns = <100>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wait-monitoring-ns = <0>;
		gpmc,wr-data-mux-bus-ns = <0>;

		/* MTD partition table */
		/* All SPL-* partitions are sized to minimal length
		 * which can be independently programmable. For
		 * NAND flash this is equal to size of erase-block */
		#address-cells = <1>;
		#size-cells = <2>;
		partition@0 {
			label = "mtd_nand";
			reg = <0x00000000 0x1 0x00000000>;
		};
	};
};

&qspi {
	status = "okay";

	spi-max-frequency = <48000000>;
	n25q512a@0 {
		compatible = "micron,n25q512a";
		spi-max-frequency = <48000000>;
		reg = <0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <1>;
		spi-cpol;
		spi-cpha;
		#address-cells = <1>;
		#size-cells = <1>;

		/* MTD partition table.
		 * The ROM checks the first four physical blocks
		 * for a valid file to boot and the flash here is
		 * 64KiB block size.
		 */

		/* ------------------------------------------------- */
		/* Reserve 1MB for MLO + U-Boot + u-Boot Environment */
		/* ------------------------------------------------- */
		partition@0 {
			label = "mtd_part1_mlo";
			reg = <0x00000000 0x00020000>;
		};

		partition@1 {
			label = "mtd_part1_uboot";
			reg = <0x00020000 0x000D0000>;
		};

		partition@2 {
			label = "mtd_part1_env";
			reg = <0x000F0000 0x00010000>;
		};

		/* ------------------------------------------------ */
		/* Reserve 11MB for PART1 zImage + DTB              */
		/* ------------------------------------------------ */
		partition@3 {
			label = "mtd_part1_zimage";
			reg = <0x00100000 0x00AC0000>;
		};

		partition@4 {
			label = "mtd_part1_dtb";
			reg = <0x00BC0000 0x00040000>;
		};

		/* ------------------------------------------------ */
		/* Reserve 8MB for the custom app                   */
		/* ------------------------------------------------ */
		partition@5 {
			label = "mtd_custom_app";
			reg = <0x00C00000 0x00800000>;
		};

		/* ------------------------------------------------ */
		/* Reserve 24MB for PART2 zImage + DTB               */
		/* ------------------------------------------------ */
		partition@6 {
			label = "mtd_part2_zimage";
			reg = <0x01400000 0x017C0000>;
		};

		partition@7 {
			label = "mtd_part2_dtb";
			reg = <0x02BC0000 0x00040000>;
		};

		/* ------------------------------------------------ */
		/* Reserve 20MB for OTHERS                          */
		/* ------------------------------------------------ */
		partition@8 {
			label = "mtd_loads";
			reg = <0x02C00000 0x01400000>;
		};
	};
};

&uart1 {
    status = "okay";
};

&uart3 {
    status = "okay";
};

&usb2 {
    dr_mode = "host";
};

&mcspi3 {
    status = "okay";
    ti,spi-num-cs = <1>;
    pinctrl-names = "default";
    pinctrl-0 = <&mcspi3_pins>;
    divio: divio@0 {
        compatible = "customspidriver";
        spi-max-frequency = <48000000>;
        reg = <0>;
        status = "okay";
    };
};

&mailbox5 {
	status = "okay";
	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
		status = "okay";
	};
	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
		status = "okay";
	};
};

&mmu0_dsp1 {
	status = "okay";
};

&mmu1_dsp1 {
	status = "okay";
};

&mmu_ipu1 {
	status = "okay";
};

&dsp1 {
	status = "okay";
	memory-region = <&dsp1_cma_pool>;
	mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
	timers = <&timer5>;
};

0 Romain Naour over 7 years ago in reply to Romain Naour

Intellectual 516 points

In dra7.dtsi:

uart1: serial@4806a000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806a000 0x100>;
interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart1";
clock-frequency = <48000000>;
status = "disabled";
};

uart2: serial@4806c000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806c000 0x100>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart2";
clock-frequency = <48000000>;
status = "disabled";
dmas = <&edma_xbar 51 0>, <&edma_xbar 52 0>;
dma-names = "tx", "rx";
};

uart3: serial@48020000 {
compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48020000 0x100>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart3";
clock-frequency = <48000000>;
status = "disabled";
dmas = <&edma_xbar 53 0>, <&edma_xbar 54 0>;
dma-names = "tx", "rx";
};

0 Yordan Kovachev over 7 years ago in reply to Romain Naour

TI__Guru**** 161600 points

I'll have a look at those and update.

Best Regards,
Yordan

0 Yordan Kovachev over 7 years ago in reply to Yordan Kovachev

TI__Guru**** 161600 points

Hi,

Sorry for the delay. I checked the uart settings and they are correct.
I am out of ideas why you might be seeing this error.

Can you explain which OpenCL example are you running? Or is this a custom program, in which case what does it do?

Best Regards,
Yordan

0 Francois Charlot over 7 years ago in reply to Yordan Kovachev

TI__Mastermind 27997 points

Hi Yordan,

I have discussed with the customer who will try to reproduce the issue on the AM572x IDK (TMDXIDK5728) so we could duplicate their setup on our side. We will get their software through Box.

Best regards,
François.

0 Yordan Kovachev over 7 years ago in reply to Francois Charlot

TI__Guru**** 161600 points

Let me know when you have some feedback.

Best Regards,
Yordan

0 Romain Naour over 7 years ago in reply to Yordan Kovachev

Intellectual 516 points

Hi,

I'm working with the customer and I'm trying to reproduce the issue on the AM572x IDK board.

I'm using the same build system (Yocto) with the same kernel and libraries version in order to reduce the difference between the two boards (see the dts attached).

The Linux kernel is started only with 512Mo of RAM (like on the customer board) using mem=512M on the kernel command line.

We don't see the problem reported initially and the offline test program run fine...

So we had a closer look to the CPU hardware and we noticed that the CPU revision may not be the same.

On the customer board, the CPU ID is XAM5718ZBOXES and on the IDK board the CPU ID is XAM5718AABCXEA.

But cpuinfo report the same value on both board (weird)

root@am5718:/ # cat /proc/cpuinfo 
processor       : 0
model name      : ARMv7 Processor rev 2 (v7l)
BogoMIPS        : 12.29
Features        : half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm 
CPU implementer : 0x41
CPU architecture: 7
CPU variant     : 0x2
CPU part        : 0xc0f
CPU revision    : 2

Hardware        : Generic DRA72X (Flattened Device Tree)
Revision        : 0000
Serial          : 0000000000000000

Do you know if the CPU hardware is really different ?

Also we noticed that the GIC are not the same

On the IDK board we have GICv2 with two arch_timer used:

# cat /proc/interrupts
           CPU0
16:          0      CBAR 32 Level     gp_timer
17:          0     GICv2 29 Edge      arch_timer
18:      25085     GICv2 30 Edge      arch_timer
22:          0      CBAR   4 Level     l3-dbg-irq
23:          0     WUGEN 10 Level     l3-app-irq
27:          0      CBAR   8 Level     omap-dma-engine
30:          0      CBAR 361 Level     43300000.edma_ccint
32:          0      CBAR 359 Level     43300000.edma_ccerrint
35:          0      CBAR 24 Level     4ae10000.gpio
68:          0      CBAR 25 Level     48055000.gpio
101:          0      CBAR 26 Level     48057000.gpio
134:          0      CBAR 27 Level     48059000.gpio
167:          0      CBAR 28 Level     4805b000.gpio
200:          1      CBAR 29 Level     4805d000.gpio
233:          0      CBAR 30 Level     48051000.gpio
266:          0      CBAR 116 Level     48053000.gpio
299:       5885      CBAR 69 Level     48020000.serial
310:         44      CBAR 251 Level     mbox_dsp1_ipc3x
335:        389      CBAR 51 Level     48070000.i2c
338:          0      CBAR 23 Level     40d01000.mmu
339:          0      CBAR 145 Level     40d02000.mmu
340:          0      CBAR 395 Level     58882000.mmu
341:          0      CBAR 396 Level     55082000.mmu
344:          0      CBAR 49 Level     4a140000.sata
349:       4882      CBAR 335 Level     48484000.ethernet
350:        749      CBAR 336 Level     48484000.ethernet
359:          0      CBAR 46 Level     4b101000.sham
360:          0      CBAR 47 Level     48090000.rng
430:          0   pinctrl 584 Edge      48020000.serial
IPI0:          0 CPU wakeup interrupts
IPI1:          0 Timer broadcast interrupts
IPI2:          0 Rescheduling interrupts
IPI3:          0 Function call interrupts
IPI4:          0 Single function call interrupts
IPI5:          0 CPU stop interrupts
IPI6:          0 IRQ work interrupts
IPI7:          0 completion interrupts
Err:          0

On the customer board, only one arch_timer using GIC:

# cat /proc/interrupts
           CPU0
16:          0      CBAR 32 Level     gp_timer
19:   44970158       GIC 27 Edge      arch_timer
22:          0      CBAR   4 Level     l3-dbg-irq
23:          0     WUGEN 10 Level     l3-app-irq
27:   34885232      CBAR   8 Level     omap-dma-engine
30:        256      CBAR 361 Level     43300000.edma_ccint
32:          0      CBAR 359 Level     43300000.edma_ccerrint
35:          0      CBAR 24 Level     4ae10000.gpio
68:          0      CBAR 25 Level     48055000.gpio
101:          0      CBAR 26 Level     48057000.gpio
134:          0      CBAR 27 Level     48059000.gpio
167:          0      CBAR 28 Level     4805b000.gpio
200:          0      CBAR 29 Level     4805d000.gpio
233:          0      CBAR 30 Level     48051000.gpio
266:          0      CBAR 116 Level     48053000.gpio
299:        907      CBAR 67 Level     4806a000.serial
300:         13      CBAR 69 Level     48020000.serial
303:          5      CBAR 251 Level     mbox_dsp1_ipc3x
323:          0      CBAR 23 Level     40d01000.mmu
324:          0      CBAR 145 Level     40d02000.mmu
325:          0      CBAR 395 Level     58882000.mmu
328:          0      CBAR 49 Level     4a140000.sata
332:          0      CBAR   1 Level     48078000.elm
333:          0      CBAR 15 Level     gpmc
335:       5186      CBAR 335 Level     48484000.ethernet
336:          0      CBAR 336 Level     48484000.ethernet
342:          0      CBAR 46 Level     4b101000.sham
343:          0      CBAR 47 Level     48090000.rng
IPI0:          0 CPU wakeup interrupts
IPI1:          0 Timer broadcast interrupts
IPI2:          0 Rescheduling interrupts
IPI3:          0 Function call interrupts
IPI4:          0 Single function call interrupts
IPI5:          0 CPU stop interrupts
IPI6:          0 IRQ work interrupts
IPI7:          0 completion interrupts
Err:          0

Finally the two board are using a very similar Linux system but we can't go further due to hardware differences.

We would like to use a second UART on the IDK board but the cpu pin are already used by a RS485 chip converter and other peripheral...

Can this information help you ?

Best regards,

Romain Naour

Fullscreen customer_like_dts_for_IDK.dts.txt Download

/*
 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
 
/ {
	model = "TI AM5718 CUSTOMIZED IDK";
	compatible = "ti,am5718-idk", "ti,am5718", "ti,dra722",
		     "ti,dra72", "ti,dra7";

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x20000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		dsp1_cma_pool: dsp1_cma@99000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x99000000 0x0 0x4000000>;
			reusable;
			status = "okay";
		};

		cmem_block_mem_0: cmem_block_mem@90000000 {
			reg = <0x0 0x90000000 0x0 0x05800000>;
			no-map;
			status = "okay";
		};
	};

	cmem {
		compatible = "ti,cmem";
		#address-cells = <1>;
		#size-cells = <0>;

		#pool-size-cells = <2>;

		status = "okay";

		cmem_block_0: cmem_block@0 {
			reg = <0>;
			memory-region = <&cmem_block_mem_0>;
			cmem-buf-pools = <1 0x0 0x05800000>;
		};
	};

	leds@1 {
		compatible = "gpio-leds";
		led@0 {
			label = "status0:red:cpu0";
			gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "cpu0";
		};

		led@1 {
			label = "status0:green:usr";
			gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led@2 {
			label = "status0:blue:heartbeat";
			gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "heartbeat";
		};

		led@3 {
			label = "status1:red:usr";
			gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led@4 {
			label = "status1:green:usr";
			gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led@5 {
			label = "status1:blue:mmc0";
			gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "mmc0";
		};
	};
};

&uart1 {
    status = "okay";
};

&usb2 {
    dr_mode = "host";
};

&uart3 {
	status = "okay";
};

&mac {
	status = "okay";
	dual_emac;
};

&cpsw_emac0 {
	phy_id = <&davinci_mdio>, <0>;
	phy-mode = "rgmii";
	dual_emac_res_vlan = <1>;
};

&cpsw_emac1 {
	phy_id = <&davinci_mdio>, <1>;
	phy-mode = "rgmii";
	dual_emac_res_vlan = <2>;
};

&qspi {
	status = "okay";

	spi-max-frequency = <76800000>;
	m25p80@0 {
		compatible = "s25fl256s1", "jedec,spi-nor";
		spi-max-frequency = <76800000>;
		reg = <0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		#address-cells = <1>;
		#size-cells = <1>;

		/* MTD partition table.
		 * The ROM checks the first four physical blocks
		 * for a valid file to boot and the flash here is
		 * 64KiB block size.
		 */
		partition@0 {
			label = "QSPI.SPL";
			reg = <0x00000000 0x000040000>;
		};
		partition@1 {
			label = "QSPI.u-boot";
			reg = <0x00040000 0x00100000>;
		};
		partition@2 {
			label = "QSPI.u-boot-spl-os";
			reg = <0x00140000 0x00080000>;
		};
		partition@3 {
			label = "QSPI.u-boot-env";
			reg = <0x001c0000 0x00010000>;
		};
		partition@4 {
			label = "QSPI.u-boot-env.backup1";
			reg = <0x001d0000 0x0010000>;
		};
		partition@5 {
			label = "QSPI.kernel";
			reg = <0x001e0000 0x0800000>;
		};
		partition@6 {
			label = "QSPI.file-system";
			reg = <0x009e0000 0x01620000>;
		};
	};
};

&mailbox5 {
	status = "okay";
	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
		status = "okay";
	};
	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
		status = "okay";
	};
};

&mmu0_dsp1 {
	status = "okay";
};

&mmu1_dsp1 {
	status = "okay";
};

&mmu_ipu1 {
	status = "okay";
};

&dsp1 {
	status = "okay";
	memory-region = <&dsp1_cma_pool>;
	mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
	timers = <&timer5>;
};

0 Yordan Kovachev over 7 years ago in reply to Romain Naour

TI__Guru**** 161600 points

I am looking into this. Note that my feedback will be delayed, because I am OoO for the holidays.

Best Regards,
Yordan

Processors

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Linux/AM5718: Error when running OpenCL example