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TMS320C6678: PLLs locked status check

Alban MICHELANGELI
Intellectual 270 points
Part Number: TMS320C6678

Hello,

I would like to know how to check the Main and DDR3 PLLs locked status a soon as their Initialization sequence has been done.

I've read in some errata that we could use Output signals RSV20 = COREPLLLOCK and RSV21 = DDR3PLLLOCK status.

But, we would like to be able to check the PLL Locked status directly by the software : 

- Is it possible to read aforementioned signals using dedicated DSP registers ?

- if not, How could we check the Locked status for Main and DDR3 PLL ?

Best regards

Alban

  • 0
    TI__Guru 65405 points
    Hi Alban,

    I've forwarded your query to the hardware experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • 0 in reply to Cvetolin Shulev-XID
    TI__Mastermind 46460 points

    Alban,

    I do not believe there is a register showing the PLL Lock status.  Once properly configured, the PLL is guaranteed to lock in the stated time.  If you need additional confirmation, you can monitor the SYSCLKOUT pin which shows the SYSCLK divided by 6.  Similarly, you can observe the DDRCLKOUT.

    Note that the process for programming the PLLs is documented in the PLL User Guide.  This sequence must be followed for robust operation.  Also note that this sequence is comprehended in the GEL file provided with CCS and it is implemented in ProcSDK.  We highly recommedn that you use the code already provided.

    Tom

  • 0 in reply to Tom Johnson 16214
    Intellectual 270 points

    Hi Tom,

    Advisory 8 - Multiple PLLs May Not Lock After Power-on Reset Issue - in the TMS320C6678 Errata documentation SPRZ334F mentions : 

    Below are the reserved pins on the device which will
    indicate the status of the main PLL lock, DDR3 PLL lock and PA PLL lock.
    • RSV20 - COREPLLLOCK
    • RSV21 - DDR3PLLLOCK
    • RSV22 - PAPLLLOCK

    Are those informations still available ?

    Best regards

    Alban MICHELANGELI

     


  • 0 in reply to Alban MICHELANGELI
    TI__Mastermind 46460 points

    Alban,

    The issue mentioned in Advisory 8 was a deficiency in the BOOTROM code.  This was corrected in the BOOTROM code implemented for PG2.0.  Also note that for PG1.0 devices, the workaround was robust.  Simply following the PLL programming sequence shown in the PLL User's Guide would result in robust, reliable operation.  This same sequence is implemented in the sample code provided in the GEL file and in the ProcSDK.

    The PLLLOCK indication can be observed on the reserved pins as stated.  That has not changed.  However, monitoring these is not required.  The PLL will lock reliably as long as you follow the prescribed procedure.

    Tom