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66AK2L06: DFE Clock and Application to Radar

David Langan
Intellectual 270 points

Part Number: 66AK2L06
Other Parts Discussed in Thread: RFSDK

I'm evaluating the 66AK2L06 for use as a processor and baseband exciter / receiver for a coherent radar application.  It seems to be nearly everything I could need in an economical package and there is a great deal of TI documentation regarding the potential for this device in radar applications.  However, going through the documentation and threads on this forum has left me with some confusion regarding the DFE.  

The device specification clearly identifies a DFE PLL which is driven by SYSCLK. Great, no problems there.  Then in Section 11.25 it indicates "DFE clock frequency of 245.76 and 368.64".  I'm having a hard time understanding what exactly this means and why that limitation would exist.  Are these maximum rates?  What if the oscillator feeding the SYSCLK does not support these frequencies?

Presume I have a precision 10 MHz source.  I use a TI PLL to increase the frequency to 100 MHz and distribute the clock to the 66AK2L06 as well as high speed TI ADC's and DAC's with digital up/down converters.  Why would I ever want/need a fractional DFE clock frequency?  It would make a great deal more sense to select 200 or 300 MHz as a DFE clock frequency and use an integer multiplier that may be supported on all 3 devices.

Perhaps the multiplier and divider values on the DFE are fixed by the RFSDK.  If so it would be very helpful to know what they are, as the ultimate DFE frequency would change relative to whatever the oscillator frequency is supplying the SYSCLK.

Any clarity on this matter would be greatly appreciated.

  • 0
    TI__Guru**** 161600 points
    We're looking into this. feedback will be posted here.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    TI__Mastermind 37500 points

    Hello 

    There are several places within the 66AK2L06, where the DFE clock rates , or DFE gated clock rates are used.

    The section on the DFE PLL, is based on specific multiplier divider ratios, the input is 122.88Mhz, the DFE PLL creates a 737.28Mhz (x6), or a 983.04Mhz (x8) clock.

    The SYSREF logic section, creates a divided clock used for processing the SYSREF signal and distributing the divided DFE PLL to the DFE and IQN blocks.

    For Class1 operation JESD204B, the SYSREF Logic resamples the SYSREF external signal to synchronize the external SYSREF to the internal DFE divided clock of 245.76Mhz or 368.64Mhz.

    The DFE and IQN utilize clock gating, for 4 baseband sample periods, and other operations.   The DFE also has clock gating to match the data transfer rate for the DFE stream to serdes digital interface.

    The serdes data transfer rate is a submultiple of the DFE divided clock 245.76, or 368.64Mhz.   In a special case. the data transfer rate is 2x the DFE divided clock.

    The RFSDK has examples of the 245.76Mhz clock for the standard LTE examples.   The adjacent market experiments design 1,2, 4 utilize the 368.64Mhz divided DFE clock.

    Regards,

    Joe Quintal