Problem in using LIDD Controller of AM1808 under uboot

I finally know why the LIDD controller stops after a third writen to the LIDD_CS0_ADDR or LIDD_CS0_DATA. I found that if the W_HOLD of the LIDD_CS0_CONF is set to '0', it will make the state machine stop. When W_HOLD is non-zero, LIDD_CS0_ADDR and LIDD_CS0_DATA can be written repeatedly without problem.

But I still cannot make the LIDD signals output on the corresponding pins, I have double checked the pinmux setting and did not find anything wrong. 

Any ideal on it is apprecated!

Colman

Colman,

On which pins are you expecting data?  Are you able to determine if the data is swapped on the pins or if it is just garbage?

-Tommy

Dear Tommy,

My code is:

const struct pinmux_config lcdc_pins[] = {
        /* MUX, value, field */
        { pinmux[16], 2, 7 },    /* Select LCD_D2 */
        { pinmux[16], 2, 6 },    /* Select LCD_D3 */
        { pinmux[16], 2, 5 },    /* Select LCD_D4 */
        { pinmux[16], 2, 4 },    /* Select LCD_D5 */
        { pinmux[16], 2, 3 },    /* Select LCD_D6 */
        { pinmux[16], 2, 2 },    /* Select LCD_D7 */
        { pinmux[17], 2, 1 },     /* Select LCD_D0 */
        { pinmux[17], 2, 0 },    /* Select LCD_D1 */
        { pinmux[18], 2, 6 },    /* Select LCD_PCLK/LIDD_RD# */
        { pinmux[19], 2, 6 },    /* Select LCD_AC_ENB_CS/LIDD_CS0# */
        { pinmux[19], 2, 1 },    /* Select LCD_VSYNC/LIDD_A0 */
        { pinmux[19], 2, 0 },    /* Select LCD_HSYNC/LIDD_WE# */
 };

...

lpsc_on(32 + 16);    // lpsc id for lcdc of am1808 is 16 of lpsc1
/* Switch the pin function */
if (davinci_configure_pin_mux(lcdc_pins, ARRAY_SIZE(lcdc_pins)) != 0) {
    printf("%s: Fail to init LCDC pins\n", __FUNCTION__);
    return;
}

...

while (1) {
     writel(0x5555, &da8xx_lcdc_regs->lidd_cs0_addr);
     writel(0xAAAA, &da8xx_lcdc_regs->lidd_cs0_data);
     putc('U');   
 }

I expect LCD_D0 to LCD_D15, LCD_VSYNC(RS), LCD_HSYNC(WE#), LCD_AC_ENB_CS#(CS0) are toggling, but all pins are not. They all not change in level, LCD_HSYNC(WE#) keeps at high level, no write cycle happen.

Regards,

Colman