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[OMAPL138] McASP Multi-channel error

tien ngoc
Intellectual 345 points
Other Parts Discussed in Thread: OMAPL138

Hello everyone,

I am working on OMAPL138 for an audio application and using McASP + EDMA for transmit/receive audio data from 2 codec (CODEC1 and CODEC2).

In my application, I always listen data from left channel of CODEC1. I sure that CODEC1 always push audio data to left channel and zero to right channel. However, sometime (approximately 5%) I receive all zeros in left channel and audio data in right channel of CODEC1.

I think there are 2 possible reasons:

-McASP got mistake. It confused left channel to right channel

-EDMA missed 1 event from McASP so first sample of left channel was gone.

Has anyone encountered such a condition? and How to fix this?

Thank in advance.

Tien.

  • 0
    TI__Guru**** 161600 points
    Hi,

    I've not seen reports of such issues.

    Can you share which SDK are you using? Also which OS RTOS or Linux?

    Best Regards,
    Yordan
  • 0
    TI__Guru** 116770 points
    It is hard to comment of MCASP issues like this if we have no insight into how you have setup the MCASP and how the audio clocking on your board is setup. We expect people to provide the following details to provide assistance with audio issues.
    processors.wiki.ti.com/.../Checklist_for_Processor_SDK_RTOS_questions_on_E2E

    Have you tried to check on the scope that the frame sync, bit clock and data occur on the correct time slot. Also make sure you have the correct AIC codec settings so the data appears on the right slot.
  • 0 in reply to Rahul Prabhu
    Intellectual 345 points
    Hi Yordan Kovachev and Rahul Prabhu ,
    Thank for reply.

    I using SYS/BIOS version 6.45 and OMAPL138_Starterware version 1.10.04.01
    Detail about my code:
    * Initialize:
    - I setup mcasp with 2 serializes, each serialize have 2 channel (Left and Right)
    - frame sync and bit clock are generated by CODEC (external)
    - I2S mode
    - Use EDMA for transfer data

    *When start:
    - Active codec for generate clock
    - Reset MCASP_GBLCTL register
    - Config McASP as I write below
    - Request EDMA channel:
    EDMA3RequestChannel (SOC_EDMA30CC_0_REGS,
    EDMA3_CHANNEL_TYPE_DMA,
    EDMA3_CHA_MCASP0_TX,
    EDMA3_CHA_MCASP0_TX,
    0);
    EDMA3RequestChannel (SOC_EDMA30CC_0_REGS,
    EDMA3_CHANNEL_TYPE_DMA,
    EDMA3_CHA_MCASP0_RX,
    EDMA3_CHA_MCASP0_RX,
    0);
    - Initialize EDMA parameter
    - Start McASP clock:
    McASPRxClkStart (SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
    McASPTxClkStart (SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
    - Enable transfer EDMA:
    EDMA3EnableTransfer (SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, EDMA3_TRIG_MODE_EVENT);
    EDMA3EnableTransfer (SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
    - Activate the serializes:
    McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
    McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
    - Check bit XDATA and active the state machine:
    while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
    McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
    McASPTxEnable(SOC_MCASP_0_CTRL_REGS);

    *When stop
    - Disable transfer of EDMA
    EDMA3DisableTransfer (SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
    EDMA3DisableTransfer (SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, EDMA3_TRIG_MODE_EVENT);
    - Stop McASP
    HWREG (SOC_MCASP_0_CTRL_REGS + MCASP_GBLCTL) = 0;
    McASPRxReset (SOC_MCASP_0_CTRL_REGS);
    McASPTxReset (SOC_MCASP_0_CTRL_REGS);
    - Free channel EDMA
    EDMA3FreeChannel (SOC_EDMA30CC_0_REGS,
    EDMA3_CHANNEL_TYPE_DMA,
    EDMA3_CHA_MCASP0_TX,
    EDMA3_TRIG_MODE_EVENT,
    EDMA3_CHA_MCASP0_TX,
    0);
    EDMA3FreeChannel (SOC_EDMA30CC_0_REGS,
    EDMA3_CHANNEL_TYPE_DMA,
    EDMA3_CHA_MCASP0_RX,
    EDMA3_TRIG_MODE_EVENT,
    EDMA3_CHA_MCASP0_RX,
    0);

    I start and stop transfer data too much and sometime (~5%) I see data of Left channel and right channel swapped. In this time, I check signal in data net and sure that data transferred in correct slot.

    Thanks.
    Tien.