DRA712: Display configuration in Jacinto 6

Raul Matos

Part Number: DRA712
Other Parts Discussed in Thread: SN65LVDS93A

Team, please address my customer's question asap:

I'm working on setting up our display with the new Jacinto board we are designing.

I would like to ask you if you can provide us any information on how to configure it and how to configure the DRM or the framebuffer since we are not familiarized with this new setup.

When we used the framebuffer in our previous board we had to configure the pixel format and color depth, do we have to set those now? And if we have to, can you please guide us to where is this located?

The setup we are using is a serializer that transforms the output of the Jacinto to LVDS to maintain the same display we were using before. The serializer is the model SN65LVDS93A. Our electrical team already contacted your team about this setup and it was validated.

Please, let me know if you need more information.

over 7 years ago

0 Yordan Kamenov over 7 years ago

TI__Mastermind 42515 points

Hi Raul,

I have forwarded your question to display experts.

Regards,
Yordan

0 Venkat Mandela over 7 years ago in reply to Yordan Kamenov

TI__Expert 5960 points

Raul,

From the data sheet, it appears that only configuration required is to

1. set the SHTDN and CLKSEL signals to desired level.
2. Configure display output with the required timings.

if (1) is being doing using GPIO's, it can be done using gpio-hog. If these lines are pulled up/down on the EVM, this step is not necessary.

For (2), please refer to

a. review.omapzoom.org/38522 for example on defining the LCD timings.
b. review.omapzoom.org/ for how to tie it to the EVM dts.

This will setup RGB pixel format with 24 bit data width.

If this does not answer your question, please provide further information.

regards,
Venkat

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DRA712: Display configuration in Jacinto 6