DM648 VideoPort capture bandwidth using 2x8bit raw data streams

Thomas said:

Is the 80MHz max datarate valid for each of the 2 channels? Can I connect two different 80MHz datastreams to VideoPort 2.A and 2.B for example?

Yes, the video ports can capture at a maximum of 80MHz and in raw mode you can have up to two 8 bit channels per port.

Thomas said:

My plan is to connect 6 8bit datastreams to 3 Videoports - using both channels each time. Did anyone have problems with such an application?

You would have to do some driver tweaking to get that sort of configuration, however from a hardware perspective it should be possible, that would mean 6 * 80MHz = 480MBps of bandwidth coming into the part which is under the 2.13GBps maximum rate of the DDR2 interface, though this is a lot of data to be moving around so depending on what else you are doing with it you could run into a bottleneck on the DDR2 interface. For example if you read the data after bringing it in from the video port you would be using almost half of the theoretical maximum DDR2 bandwidth (480 * 2 = 960MBps).

Hi,

I'd also like to open this thread again...

My system requires:
6x 8bit cameras at 80MBit/sec (netto) -> Videoport -> DDR (data buffering) -> forward buffered data to PC on PCI

The incoming data is forwarded to a PC through PCI (66MHz -> PCI to PCIe bridge) "as fast as possible". I measured more than 100MB/sec throughput on a DM642 prototype with 33MHz 32bit PCI. I wanted to use 66MHz 32bit PCI on the DM648 and calculated with about 150MB/s. According to a recent posting, DM648 is really slow in terms of PCI throughput.

Whats the imapct of PCI communication to Videoport->DDR2 bandwidth? I read about maximum DDR bandwidth of 2128MB/sec and thought that I'd be anyhow limited by the 480MB/s Videoport bandwidth and that the additional 150MB/s would be possible... My application does not read the image data at this point. So I calculated 6*80 (write to DDR) + 150 (read from DDR) which are about 700MB/s and far off the >2000 MB/s max. bandwidth.

My application will mainly run in L2RAM. There might be some DDR-access for example for logging but I dont expect relevant ammount of DDR access from that.

Additionaly I was planning to do linked EDMA transfers to 'scale' the image while it is grabbed. Each Videoport-Fifo EDMA event first triggers a VP->DDR transfer. The EDMA ready event triggers another EDMA that copies every 2nd or 4th pixel of every 2nd or 4th line to a second buffer in DDR Ram to get a 'scaled image' in lower quality that is sent to the PC through PCI (and forwarded from there to a second PC over Ethernet). This will not be required for all cameras. But if I need it for 3 cameras this would cause additional 3x80MB read (I think that reading one byte and dropping one byte requires to read everything) and 3x40MB write bandwidth.

what about this scenario? will DDR read access by EDMA reduce the bandwidth if the access is of the type 'copy 1 byte and skip 1 byte'?

best regards,

Thomas

Hi,

and what if using the DM642 was an option? Theoretically it has 3x2 Videoports that operate at 80MHz. But only 133MHz SDRAM. Is DM642 EMIF capable to store 480MB/s into the SDRAM? Plus serving 66MHz PCI with about 150MB/s, plus a few other SDRAM accesses from the application (will be more than on DM648 since it has a quite small internal RAM).

Would it be possible to use 512MB SDRAM on the DM642?

How long will the DM642 be available? I thought that is already quite old and DM648 is its succesor... I'm not sure if we should base a new design on a DM642...

bye,

Thomas

Thomas said:

But only 133MHz SDRAM. Is DM642 EMIF capable to store 480MB/s into the SDRAM? Plus serving 66MHz PCI with about 150MB/s, plus a few other SDRAM accesses from the application (will be more than on DM648 since it has a quite small internal RAM).

Would it be possible to use 512MB SDRAM on the DM642?

The maximum the EMIF SDRAM interface can possibly transfer is 1064MBytes/sec. This assumes zero overhead and a full bus-width transfer every 7.5ns (133MHz).  I think that with maximum efficiency your 480MB/s number might be achievable, but with normal system traffic I am not sure if 480MB/s is a realistic goal. I am trying to find some documentation to back this up but I am not sure if any true throughput numbers exist.

You can access 512MB of SDRAM, but this requires the use of two separate CE spaces as each chip select covers a range of 256MBytes.

Thomas said:

How long will the DM642 be available? I thought that is already quite old and DM648 is its succesor... I'm not sure if we should base a new design on a DM642...

 The DM642 has indeed been around for many years but at this point there are no immediate plans to end-of-life this part. Note that the software is not likely to change nor is it likely to see a new silicon spin, but the device itself will likely be sold for years to come. I cannot guarantee that it will be so you may want to factor that into your decision.