C674x USB0 Peripheral when to clear FIFONOTEMPTY bit in PERI_TXCSR

Hi Peter,

Yes you are correct. The only time you need to flush the FIFO is when the FIFONOTEMPTY is set, which is an indication of a data presence in the FIFO, and you do not want to send that data out. Then you would flush the FIFO by setting the FLUSHFIFO bit.  There are times that you load the FIFO with data and you change your mind. You can ensure that the data is not sent by flushing the FIFO. Other than that, it is also used as an indication for the presence of data in the FIFO during debug purposes. For e.g. you may think that the data has been driven out but the remote device has not acknowledged and the data remains in the FIFO and you also have not received an interrupt. At this time, this bit gets set and remain set until an ACK is received and can be used as a quick high level debug indication that packet transmission has not completed or some thing is wrong ... etc.

Best regards, Zegeye

Thanks for the Reply Zegeye,

I presume from your answer therefore that the documentation is incorrect in stating that I "should clear the [FIFONOTEMPTY] bit", but rather it is an indication bit, that can be useful.

Peter

Hello,

I also independently stumbled accross this point and would appreciate if the answer could be made less vague. That is, does the user ever have to write FIFONOTEMPTY?

Kind regards,

Mark

Hi,

FIFONOTEMPTY bit gets set when there is data in the FIFO. What it really means that if the FIFO pointer is pointing to an offset other than the starting offset location. If this bit is set, then it means you have data inside the FIFO that has not been attended yet. When you finish unloading data from a Receive FIFO or data placed for transmition in a Transmit FIFO is driven out, the controller will clear the bit automatically. Application s/w can not directly control this field. You usually use this bit for Debugging or your DMA got into a hung situation and you flush the FIFO, then the controller will clear this bit field.

Best regards, Zegeye

Hi Zegeye,

I have a question regarding your advice "Btw, it is not a good idea to invoke FIFO reset when no data is present in the FIFO."

I think it's also true if we select double buffer for TXFIFO setting. In this case we need to set PERI_TXCSR.FLUSHFIFO twice to clear the TXFIFO completely. But I wonder how I can check whether no data is present in the FIFO or not.

Could you let me know how to do this?

Best regards,

Shibata

Hi,

Yes, you are correct. I recommend not invoking FIFO reset unless needed. If FIFO is empty and you invoke a RESET, it will throw away the next packet you load onto the FIFO. The FIFONOTEMPTY bit will be set until the FIFO allocated is empty (that is, when the internal pointer within the FIFO is not pointing to the start of the FIFO). If you are using double buffering, then you will have two sets of pointers used and based on the FIFO you are accessing at the moment, the FIFONOTEMPTY bit field will reflect the status of data presence within the FIFO or not.

Best regards, Zegeye

Hi Zegeye,

Thank you for your prompt reply. Now I fully understand.

Best regards,

Shibata