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OMAPL138 Watchdog

Other Parts Discussed in Thread: OMAPL138, AM1808, TPS65070

Hello,

I've got some questions about the watchdog timer (timer1) on the omapl138. In sprufm5b.pdf in chapter 2.2 it is written "In order to fully function in watchdog timer mode, the timer must be connected to the device hardware reset signal.". Does this mean that we have to connect TM64P1_OUT12 to /RESET if we want the device to reset itself upon a watchdog timeout? 

We don't want the device to reset itself upon a watchdog timeout because we have to reset some other parts of the system manually by software before the omapl138 goes into reset. Is it possible to use the watchdog timer in watchdog mode just to generate an interrupt on arm side? TM64P1_OUT12 is not connected to /RESET in our system.

Thanks

  • Hi Marc

    Marc said:
    "In order to fully function in watchdog timer mode, the timer must be connected to the device hardware reset signal.". Does this mean that we have to connect TM64P1_OUT12 to /RESET if we want the device to reset itself upon a watchdog timeout? 

    This actually implied having the timer "internally" connected to signal that would cause a device reset. User does not have to the timer pin to the device /RESET pin. The statement was intended to make the user guide more "generic" to prompt user to look at the datasheet to see which of the on chip timers as the WDT functionality. In case of OMAPL138 it is Timer 1.

    Marc said:
    We don't want the device to reset itself upon a watchdog timeout because we have to reset some other parts of the system manually by software before the omapl138 goes into reset. Is it possible to use the watchdog timer in watchdog mode just to generate an interrupt on arm side? TM64P1_OUT12 is not connected to /RESET in our system.

    Hmm...that will still not work, a WDT time out will initiate a Power on Reset , as explained in the OMAPL138 datasheet  Section 6.4.1. A WDT time out is usually envisioned to be a fatal condition that will cause the entire device to be reset and additionally it can initiate a board level reset , if the RESETOUT signal is made use to connect to other on board components. If you can elaborate some more on your intended use-case maybe alternative suggestions can be made, however it would seem like if you don't want the WDT to cause a reset on the device , then you could use simply use a GP timer and if its period is not updated within x amount of time, you could have a timer time out interrupt be send to ARM and let ARM do the house keeping as required in your system?

    Regards

    Mukul

  • Hi Mukul,

    thanks for your fast answer. The reset inputs of the other parts of our system are connected to output pins of the omapl138. E.g. before the omapl138 is reset, we have to reset these systems by setting the ports to low. The omapl138 itself can be reset by another output port which is connected to a reset controller. It seems as if we have 3 possibilities:

    1. Use a general purpose timer interrupt and reset the subsystems as well as the omapl138 manually.

    2. Use the watchdog timer which resets the omapl138 immediately upon a timeout. After the new startup we can reset the subsystems manually.

    3. Use a watchdog timer which resets the omapl138 immediately upon a timeout. Use the RESETOUT pin and reset the subsystems via hardware logic.

    Any other suggestions??

    Could you tell me where I can find the statement "A WDT time out is usually envisioned to be a fatal condition that will cause the entire device to be reset and additionally it can initiate a board level reset , if the RESETOUT signal is made use to connect to other on board components." ? Your link doesn't semm to work.

     

    Thank you

     

     

  • One additional question. How can we see if a reset has been triggered by the watchdog? Is there a flag which we can read out after the system has started up again?

  • Marc

    Thanks for providing the clarification on your use-case

    Seems like all the options that you have listed should be viable, with option 3 typically being the most common. If I can think of others, I will let you know.  I have fixed the link in my previous post, it is just a link to the datasheet so that you could quickly get to section that talks about POR.

    It is not specifically stated anywhere that WDT is for fatal conditions, but usually that is what most customers use it, where in the software has gone astray and would not allow servicing the WDT counters in time , and in such cases it is usually expected that the device should be reset.

    Marc said:
    How can we see if a reset has been triggered by the watchdog? Is there a flag which we can read out after the system has started up again?

    I am not sure if there is a register that specifically calls out that the last reset was a WD reset. However, there is a register in the PLLC , RSTTYPE that lets you distinguish between external reset vs power on reset.

    Details in the system guide

    http://focus.ti.com/lit/ug/sprugm7d/sprugm7d.pdf

    Pg 91, section 8.3.3.

    Hope this helps.
    Regards

    Mukul

     

  • Hello,

    I had a closer look at the register in the pllc which stores the type of the last reset. After powering on the board the power on reset bit in the register is set. When the watchdog triggers a reset the same bit is set since the watchdog also triggers a power on reset as mentioned in sprs586b chapter 6.4. So we have no chance to see if the last reset was triggered by the watchdog, right? We want to know this in order to to some error reporting. Otherwise the device does watchdog resets an we don't even recognize this.

    Just another question about ddr2 memory content. What happens with ddr2 memory content upon a warm reset and upon a power on reset? Is it maintained? The content of internal  memory is maintained upon a warm reset and is not maintained upon a power on reset as mentionend sprs586b chapter 6.4.

    Thanks so far

  • Hi Marc

    Marc said:
    So we have no chance to see if the last reset was triggered by the watchdog, right?

    That is correct, as I mentioned in my previous post the PLL register will only allow distinguishing between POR vs warm reset, and since a WD time out initiates a POR, there is no way to distinguish between a regular POR vs a WD time out initiated POR.

    Marc said:
    We want to know this in order to to some error reporting. Otherwise the device does watchdog resets an we don't even recognize this.

    This looks a bit impossible to achieve within the domains of the OMAPL1x device initiated watch dog time out.

    Marc said:
    Just another question about ddr2 memory content. What happens with ddr2 memory content upon a warm reset and upon a power on reset? Is it maintained? The content of internal  memory is maintained upon a warm reset and is not maintained upon a power on reset as mentionend sprs586b chapter 6.4.

    No, since both warm and power on reset, reset the entire internal logic of the device, this implies resetting the DDR2/mDDR controller configuration registers, and the clocks to memory controller and memory itself will be reset, the contents of the memory will not be guaranteed to be preserved on unplanned resets. The only way to maintain the contents of the DDR2/mDDR memory would be to put it in self refresh mode prior to reset etc.

    Regards

    Mukul

  • Hi,

    I am working with am1808 processor and made a separate prototype and used the logicPD schematics.
    The board is working, but in some time there is suddenly processor gets hang-up. we are not getting any LCD signals
    But all the voltages which are coming from the TPS65070 power IC it is driving all the signals.
    But finally processor out signals are not coming, when I restart the processor again it starts booting and
    working in as normal. And again the same issue comes in randomly .
    what could be the reason, how come the processor gets hang or RESET.
    Please need your suggestions.

    Thanks,
    Francis