Tool/software: Code Composer Studio
further detail:
For some design reason, I just can use LaneC and Lane D of all four lanes(LaneA,LaneB,LaneC,LaneD).
question detail:
I want to configure 6678's SRIO as 1x mode, and this 1x port uses LaneC .like figure below:
And my changes to the device_srio_loopback.c(PATH:C:\ti\pdk_C6678_1_1_2_6\packages\ti\drv\srio\device\device_srio_loopback.c)
is as below:
// set port 2 as normal mode CSL_SRIO_SetNormalMode(hSrio, 2); // configure cfgPLL and rx&tx CSL_BootCfgSetSRIOSERDESConfigPLL (0x229); CSL_BootCfgSetSRIOSERDESRxConfig (2, 0x00440495); CSL_BootCfgSetSRIOSERDESTxConfig (2, 0x00180795); // TLM port base routing configration CSL_SRIO_SetTLMPortBaseRoutingInfo(hSrio, 2, 1, 1, 1, 0); CSL_SRIO_SetTLMPortBaseRoutingInfo(hSrio, 2, 2, 1, 1, 0); CSL_SRIO_SetTLMPortBaseRoutingInfo(hSrio, 2, 3, 1, 1, 0); CSL_SRIO_SetTLMPortBaseRoutingInfo(hSrio, 3, 0, 1, 1, 0); CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(hSrio, 2, 1, DEVICE_ID2_16BIT, 0xFFFF); CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(hSrio, 2, 2, DEVICE_ID3_16BIT, 0xFFFF); CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(hSrio, 2, 3, DEVICE_ID4_16BIT, 0xFFFF); CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(hSrio, 3, 0, DEVICE_ID2_8BIT, 0xFF); /* Set the PLM Port Silence Timer. */ CSL_SRIO_SetPLMPortSilenceTimer (hSrio, 2, 0x2); /* TODO: We need to ensure that the Port 0 is configured to support both * the 2x and 4x modes. The Port Width field is read only. So here we simply * ensure that the Input and Output ports are enabled. */ CSL_SRIO_EnableInputPort (hSrio, 2); CSL_SRIO_EnableOutputPort (hSrio, 2); /* Set the PLM Port Discovery Timer. */ CSL_SRIO_SetPLMPortDiscoveryTimer (hSrio, 2, 0x2); /* Reset the Port Write Reception capture. */ CSL_SRIO_SetPortWriteReceptionCapture(hSrio, 2, 0x0); // configure path mode as mode 0 CSL_SRIO_SetPLMPortPathControlMode (hSrio, 2, 0); // check port ok status while (CSL_SRIO_IsPortOk (hSrio, 2) != TRUE);
After all these above,I can see port2 ok,but if I use the function blow to read or write (NREAD, NWRITE) to FPGA,there will be
nothing happen.
read function:
// LSUtransfer structure
lsuTransfer0.rapidIOMSB = 0x0;
lsuTransfer0.doorbellValid = 0;
lsuTransfer0.intrRequest = 1;//0b1- An interrupt is requested upon completion of command
lsuTransfer0.supInt = 0;//n0o Interrupt will be generated on good completion as well
lsuTransfer0.xambs = 0;
lsuTransfer0.priority = 0;
lsuTransfer0.outPortID = 0;
lsuTransfer0.idSize = 1;
lsuTransfer0.srcIDMap = 0;//0b0000 j Uses contents of RIO_DEVICEID_REG0 register
lsuTransfer0.dstID = 0x0077;
lsuTransfer0.ttype = 4;
lsuTransfer0.ftype = 2;
lsuTransfer0.hopCount = 0;
lsuTransfer0.doorbellInfo = 0;
// use LSU2 to do the transmit
void srio_read(unsigned int dsp_addr,unsigned int byte_cnt,unsigned int rpio_addr)
{
int print = 0;
unsigned char context;
unsigned char transID;
unsigned char count;
unsigned char compCode = 1;
unsigned char contextBit = 0;
unsigned int lsu2_reg6;
// CSL_SRIO_GetLSUShadowRegs (hSrio, 0, &count);//փսShadowRegsքcount,Ȼ۳ҢûԐŃ4ԃС
CSL_SRIO_GetLSUShadowRegs (hSrio, 2, &count);
do{
lsu2_reg6=*(volatile unsigned int*)0x02900D50;//LSU2_REG6,在datasheet里是LSU3_REG6
}while((lsu2_reg6 & 0xc0000000) != 0);
// CSL_SRIO_GetLSUContextTransaction (hSrio,0, &context, &transID);
CSL_SRIO_GetLSUContextTransaction (hSrio,2, &context, &transID);
lsuTransfer0.dspAddress = dsp_addr;
lsuTransfer0.bytecount = byte_cnt;
lsuTransfer0.rapidIOLSB = rpio_addr;
CSL_SRIO_SetLSUTransfer (hSrio, 2, &lsuTransfer0);
do
{
CSL_SRIO_GetLSUCompletionCode (hSrio, 2, transID, &compCode, &contextBit);
}while(compCode!=0 && contextBit!=context);
}
Which step I have done is wrong?
