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AM3358: EDMA shadow region offsets

Daniel Brown
Intellectual 870 points
Part Number: AM3358

I see on page 1504 of the TRM a reference to the Shadow Region offsets but it is not entirely clear what the offset are for the regions after ShadowReg 0.
Are the regions in this sequence, ShadowReg1 offset = 2200h, ShadowReg2 offset = 2400h, etc ShadowReg7 offset = 2E00?

In other words, offset = 2000h + (200h * n) where n = 0 to 7?

  • 0
    TI__Guru**** 393215 points
    Which document are you referring to? There is nothing of this kind mentioned on page 1504 of the AM335x TRM Rev. P.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 870 points
    Sorry, that was the page in the revision I had downloaded. On Rev P, it is page 1595.
  • 0 in reply to Daniel Brown
    TI__Guru**** 393215 points
    Thanks, I see now what you mean. I agree that this is unclear and it seems a table is missing from the TRM. I have notified the factory team. They will respond here.

    NOTE: On AM335x devices the channel controller only supports 4 shadow regions 0-3. See section 11.1.2.2 of the TRM.
  • 0
    TI__Guru* 83935 points
    Hi Daniel
    Yes your interpretation is correct. Shadow Regions start from an offset of 2000h from the EDMA CC baseline address and every shadow region space is at an offset of 200h.
    The TRM could be updated to reflect this for clarity. I will file a literature bug for the TRM team to disposition appropriately.

    For a better visual, you can look at the following TRM
    www.ti.com/.../spruh77c.pdf
    Pg 665/

    The EDMA3 IP is the same across several of our processors with slight differences in parameterization and channel count etc.

    Hope this helps.
    Regards
    Mukul
  • 0 in reply to Mukul Bhatnagar
    Intellectual 870 points

    Thank you. Are there really only 4 shadow regions in the AM3358? The TRM mentions seven regions even going so far as to mention the address offset of the last (7th) region.

  • 0 in reply to Daniel Brown
    TI__Guru**** 393215 points
    Yes, this is clearly stated in section 11.1.2.2 of the TRM.
  • 0 in reply to Daniel Brown
    TI__Guru* 83935 points
    In addition to Biser's response , to be completely accurate the EDMA memory map on AM335x does have all 8 regions and associated registers available.
    However the concept of shadow regions is really there as stated in the TRM for multiple EDMA "programmers" , this is primarily to facilitate use of EDMA3 in hetero or mutli core devices, where each CPU or programmer (upto 8) can "own" a different shadow region.
    The way this is "mapped" to a given CPU/programmer is by routing the EDMA CC shadow region interrupt to a specific cores interrupt controller (hardwired in chip design)

    Snapshot from the TRM
    The EDMA3 channel controller divides its address space into eight regions. Individual channel resources are assigned to a specific region, where each region is typically assigned to a specific EDMA programmer. You can design the application software to use regions or to ignore them altogether.

    On AM335x there are essentially 3 "programmers" A8, the cortex M3 that does power management ( this is really not intended to be used as a general purpose M3 and is not envisioned to directly program the EDMA) and the PRU-ICSS , 4 th region is not mapped to anything.

    So for all practical purposes you really can stick to global region or Shadow Region 0 for most use-cases.

    Regards
    Mukul