Tool/software: Linux
DRA7xx MII with TJA1100
Hi Experts,
I use DRA7xx customer's board with TJA1100 Ethernet PHY configure on MII mode.
SDK version is 6AM.1.3, follow this link: omapedia.org/.../6AM.1.3_Release_Notes
As customer description, TJA1100 works if processor Ethernet interface is configure as MII mode, there is no need to use specific TJA1100 driver.
I try to configure Ethernet to MII mode on U-Boot and Kernel, but seems not right.
I can use mii command to read PHY register, but U-Boot log shows could not find PHY:
Net: Could not get PHY for ethernet@48484000: addr 3
eth0: ethernet@48484000
I use ifconfig command can see there is a eth0 device, but Kernel lod shows:
[ 27.717882] net eth0: initializing cpsw version 1.15 (0)
[ 27.723239] net eth0: initialized cpsw ale version 1.4
[ 27.729293] net eth0: ALE Table size 1024
[ 27.736542] libphy: PHY 48485000.mdio:03 not found
[ 27.741365] net eth0: phy "48485000.mdio:03" not found on slave 0, err -19
As U-Boot / Kernel log, seems DRA7x can not find PHY.
I've check the TJA1100 register and H/W configuration, PHY address is 0b11, so I just modify the following setting on U-Boot / Kernel:
1. Pin Mux: modify default RGMII interface to MII, and modify MDIO pins from (V1, U4) to (D3, F6).
2. PHY ID: default cpsw_emac0 use 0 for phy_id in device tree setting, modify 0 to 3.
3. PHY MODE: modify default "rgmii" to "mii"
Here are my modifiction for U-Boot and Kernel device tree:
U-Boot mux_data.h
//Remove original MDIO define(V1,U4), add new MDIO define (D3,F6).
#if 0
{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
{MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
#else
{VIN2A_D10, (M3 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* vin2a_d10.mdio_mclk */
{VIN2A_D11, (M3 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* vin2a_d11.mdio_d */
#endif
//Remove original RGMII define, add new MII define.
#if 0
{RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
{RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
{RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
{RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
{RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
{RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
{RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
{RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
{RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
{RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
#else
{MDIO_D, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* mdio_d.mii0_txer */
{UART3_RXD, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* uart3_rxd.mii0_rxdv */
{UART3_TXD, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* uart3_txd.mii0_rxclk */
{RGMII0_TXC, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.mii0_rxd3 */
{RGMII0_TXCTL, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},/* rgmii0_txctl.mii0_rxd2 */
{RGMII0_TXD2, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.mii0_rxer */
{RGMII0_TXD1, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.mii0_rxd1 */
{RGMII0_TXD0, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.mii0_rxd0 */
{RGMII0_RXC, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.mii0_txclk */
{RGMII0_RXCTL, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},/* rgmii0_rxctl.mii0_txd3 */
{RGMII0_RXD3, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.mii0_txd2 */
{RGMII0_RXD2, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.mii0_txen */
{RGMII0_RXD1, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.mii0_txd1 */
{RGMII0_RXD0, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.mii0_txd0 */
#endif
U-Boot dra7-evm.dts
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
0x240 (PIN_INPUT | MUX_MODE3) /* mdio_d.mii0_txer */
0x248 (PIN_INPUT | MUX_MODE3) /* uart3_rxd.mii0_rxdv */
0x24c (PIN_INPUT | MUX_MODE3) /* uart3_txd.mii0_rxclk */
0x250 (PIN_INPUT | MUX_MODE3) /* rgmii0_txc.mii0_rxd3 */
0x254 (PIN_INPUT | MUX_MODE3) /* rgmii0_txctl.mii0_rxd2 */
0x25c (PIN_INPUT | MUX_MODE3) /* rgmii0_txd2.mii0_rxer */
0x260 (PIN_INPUT | MUX_MODE3) /* rgmii0_txd1.mii0_rxd1 */
0x264 (PIN_INPUT | MUX_MODE3) /* rgmii0_txd0.mii0_rxd0 */
0x268 (PIN_INPUT | MUX_MODE3) /* rgmii0_rxc.mii0_txclk */
0x26c (PIN_INPUT | MUX_MODE3) /* rgmii0_rxctl.mii0_txd3 */
0x270 (PIN_INPUT | MUX_MODE3) /* rgmii0_rxd3.mii0_txd2 */
0x274 (PIN_INPUT | MUX_MODE3) /* rgmii0_rxd2.mii0_txen */
0x278 (PIN_INPUT | MUX_MODE3) /* rgmii0_rxd1.mii0_txd1 */
0x27c (PIN_INPUT | MUX_MODE3) /* rgmii0_rxd0.mii0_txd0 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 */
0x240 (MUX_MODE15)
0x248 (MUX_MODE15)
0x24c (MUX_MODE15)
0x250 (MUX_MODE15)
0x254 (MUX_MODE15)
0x25c (MUX_MODE15)
0x260 (MUX_MODE15)
0x264 (MUX_MODE15)
0x268 (MUX_MODE15)
0x26c (MUX_MODE15)
0x270 (MUX_MODE15)
0x274 (MUX_MODE15)
0x278 (MUX_MODE15)
0x27c (MUX_MODE15)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
0x190 (PIN_OUTPUT_PULLUP | MUX_MODE3) /* vin2a_d11.mdio_d */
0x194 (PIN_INPUT_PULLUP | MUX_MODE3) /* vin2a_d10.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
0x190 (MUX_MODE15)
0x194 (MUX_MODE15)
>;
};
&mac {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
dual_emac;
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <3>;
phy-mode = "mii";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii";
dual_emac_res_vlan = <2>;
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
};
Kernel dra7-evm.dts
&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
};
/*WPI Roger++++++++++++*/
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <3>;
phy-mode = "mii";
};
Can anyone tell me if I got something wrong on configure MII interface on DRA7xx.
Thanks a lot.
Best Regards,
Wayne Kuo
