RTOS/PROCESSOR-SDK-AM57X: McSPI Slave device not responding

Tool/software: TI-RTOS

I currently have a SPI interface to a slave device working from the AM57xx, using GPIO lines and bit-banging. I'm "migrating" that to the PDK MCSPI driver, but the slave device no longer responds to commands sent to it. My application is running on IPU1 (dual-M4 cores), with SYS/BIOS 6.46.4.53 and am57xx PDK 1.0.6. I can see the CS, MOSI, and MISO lines on a logic analyzer, and I'm concerned about short "spikes" on the CS signal when transferring multiple bytes. I'm also not sure about the initialization values, since I've seen a number of different values.

Here's my initialization:

void vSpi_eInitialize(void)
{
    CSL_l4per_cm_core_componentRegs *l4PerCmReg = (CSL_l4per_cm_core_componentRegs *)(CSL_MPU_L4PER_CM_CORE_REGS + Du32Ipu_IOMMU_Offset);

    // SPI1 Clock Enable
    CSL_FINST(l4PerCmReg->CM_L4PER_MCSPI1_CLKCTRL_REG, L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI1_CLKCTRL_REG_MODULEMODE, ENABLE);

    // Wait for SPI peripheral to start
    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI1_CLKCTRL_REG_IDLEST_FUNC !=
              CSL_FEXT(l4PerCmReg->CM_L4PER_MCSPI1_CLKCTRL_REG,
                       L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI1_CLKCTRL_REG_IDLEST
                      )
         );

    // SPI1_SCLK
    // NOTE: For the spim_sclk signals to work properly, the INPUTENABLE bit of the appropriate
    //  CTRL_CORE_PAD_x registers should be set to 0x1 because of retiming purposes.
    HW_WR_REG32((Du32Spi_CORE_PAD_IO_REGISTERS_BASE + CTRL_CORE_PAD_SPI1_SCLK_OFFSET),
                (0x000F0000));  // SLEW_CONTROL_SLOW | INPUTENABLE_RECEIVE_ENABLED | PULLTYPESELECT_PULLUP | PULLUDENABLE_ENABLED | MUXMODE_SPI1

    // SPI1_D1 - Rx
    HW_WR_REG32((Du32Spi_CORE_PAD_IO_REGISTERS_BASE + CTRL_CORE_PAD_SPI1_D1_OFFSET),
                (0x000F0000));  // SLEW_CONTROL_SLOW | INPUTENABLE_RECEIVE_ENABLED | PULLTYPESELECT_PULLUP | PULLUDENABLE_ENABLED | MUXMODE_SPI1

    // SPI1_D0 - Tx
    HW_WR_REG32((Du32Spi_CORE_PAD_IO_REGISTERS_BASE + CTRL_CORE_PAD_SPI1_D0_OFFSET),
                (0x000B0000));  // SLEW_CONTROL_SLOW | PULLTYPESELECT_PULLUP | PULLUDENABLE_ENABLED | MUXMODE_SPI1

    // SPI1_CS0
    HW_WR_REG32((Du32Spi_CORE_PAD_IO_REGISTERS_BASE + CTRL_CORE_PAD_SPI1_CS0_OFFSET),
                (0x000B0000));  // SLEW_CONTROL_SLOW | PULLTYPESELECT_PULLUP | PULLUDENABLE_ENABLED | MUXMODE_SPI1

    // SPI1_CS1
    HW_WR_REG32((Du32Spi_CORE_PAD_IO_REGISTERS_BASE + CTRL_CORE_PAD_SPI1_CS1_OFFSET),
                (0x000B0000));  // SLEW_CONTROL_SLOW | PULLTYPESELECT_PULLUP | PULLUDENABLE_ENABLED | MUXMODE_SPI1

    // SPI1_CS2
    HW_WR_REG32((Du32Spi_CORE_PAD_IO_REGISTERS_BASE + CTRL_CORE_PAD_SPI1_CS2_OFFSET),
                (0x000B0000));  // SLEW_CONTROL_SLOW | PULLTYPESELECT_PULLUP | PULLUDENABLE_ENABLED | MUXMODE_SPI1

    /* Configure xbar connect for MCSPI3: IPU1_IRQ_60 (reserved) mapped to MCSPI3 intr */
    CSL_xbarIrqConfigure (CSL_XBAR_IRQ_CPU_ID_IPU1,
                          IPU_IRQ_MCSPI1_IRQ,
                          CSL_XBAR_MCSPI1_IRQ);

    // Modify the default SPI configurations
    SPI_v1_HWAttrs spi_cfg0;
    SPI_socGetInitCfg(0, &spi_cfg0);

    spi_cfg0.baseAddr = CSL_IPU_MCSPI1_REGS + Du32Ipu_IOMMU_Offset;
    spi_cfg0.chMode = MCSPI_MULTI_CH;
    spi_cfg0.enableIntr = false;    // polling mode
    spi_cfg0.chnCfg[0].dataLineCommMode = MCSPI_DATA_LINE_COMM_MODE_6;  // D1 is Rx; D0 is Tx
    spi_cfg0.chnCfg[1].dataLineCommMode = MCSPI_DATA_LINE_COMM_MODE_6;
    spi_cfg0.chnCfg[2].dataLineCommMode = MCSPI_DATA_LINE_COMM_MODE_6;

    SPI_socSetInitCfg(0, &spi_cfg0);

    MCSPI_init();
}

and the transfer method:

void vSpiDrv_eTransferBytes(MCSPI_Handle stSpiHandle, TU8 *pucTxBuffer, TU8 *pucRxBuffer, TU8 ucByteCount)
{
    SPI_Transaction transaction;
    transaction.count = ucByteCount;
    transaction.rxBuf = pucRxBuffer;
    transaction.txBuf = pucTxBuffer;

    Bool retVal = MCSPI_transfer(stSpiHandle, &transaction);
    if (false == retVal)
    {
        System_printf("uc_iTransferByte error occurred in SPI transfer\n");
    }

//    System_printf("MCSPI_transfer returned transaction status = %d\n", transaction.status);
}

Any ideas for what else I can check would be appreciated.

Thanks,

    Mike