Hi,
I use DSP Bios on a DM648 (EVM648 board). In the DSP BIOS Configurator, several settings affect the behaviour of the timer:
System->Global Settings->BoardClock (33MHz)
System->Global Settings->DSP Speed (CLKOUT) - (693MHz - I use PLL multiplier 21)
According to the DM648 manual (sprs372), chapter 6.3.5 'Power and Clock Domains', the Timer runs at 1/6 of the system clock. The default value at Scheduling->CLK->input frequency is the full clock rate.
It seems that DSP BIOS CLK Api functions use the CLKOUT setting instead of the correct CLKOUT/6. CLK_countspms for example returns 693000 instead of 115500.
Why? Is this a bug in my configuration?
Using the default setup leads to PRD functions being called at 1/6 of the set time - it seems that not just the return of the CLK functions are wrong.
Manually setting the CLK->Input Frequency to 115500 and CLK->PRD Register to 115500 is required to have the PRDs called in the correct
frequency - but still the api functions return the wrong values.
What is the 'normal' way you use to setup the Timers? Let DSP Bios configure the Timer and 'correct' the returned values afterwards or setup the timers like in the PSP example manually?
bye,
Thomas