EMIFA SDRAM interface

Prad

Expert 1125 points

Other Parts Discussed in Thread: OMAP-L137

Hi,

A basic question about EMIFA.

If CS0 is used for SDRAM Memory, can CS4,CS5 still be used for other devices.

Thankyou in advance.

over 15 years ago

0 tlee over 15 years ago

TI__Guru 62975 points

Prad,

The other chip select signals can be used for asynch memories, but there may be routing issues to consider if multiple memories are sharing the EMIFA bus pins.

-Tommy

0 Prad over 15 years ago in reply to tlee

Expert 1125 points

Hello Tommy,

Thankyou,

If possible could you please let me know what would be the issues in breif,

and is there there any way to solve that.

Regards

Prad.

0 tlee over 15 years ago in reply to Prad

TI__Guru 62975 points

Prad,

The datasheet places a limitation on the maximum number of memory components you can share on the EMIFA bus without external signal buffers. Also, SDRAM requires regular memory refreshes so you will need to use an SDRAM that support self-refresh if asynch memory is to be used at the same time.

-Tommy

0 Prad over 15 years ago in reply to tlee

Expert 1125 points

Hello Tommy,

I think SDRAM uses CAS and RAS pins, but these pins are multiplexed with CS4 and CS5,

In this case if SDRAM is used we cannot use CS4 and CS5?

Is this the limitation what you are saying?

and in our case we need to use SDRAM, FPGA or CPLD, Flash, Fram devices with EMIFA interface.

Please let me know what could be best way.

Thankyou,

Prad.

0 tlee over 15 years ago in reply to Prad

TI__Guru 62975 points

Prad,

Yes, this is a potential issue. What device are you using?

-Tommy

0 Prad over 15 years ago in reply to tlee

Expert 1125 points

We are using OMAP-L137.

0 tlee over 15 years ago in reply to Prad

TI__Guru 62975 points

Would you be able to limit your SDRAM usage to just EMIFB and use only the asynch/FPGA components on EMIFA?

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EMIFA SDRAM interface