AM3352: MMC1 timing characteristics clarification

Hi,

Please specify which tables and parameters from the AM335x Datasheet Rev. J are these.

By the way, what is the purpose of these measurements? I am certain that they are not made under conditions, identical to those used for device characterization.

Is this resolved? If so, please close the thread.

Hi Biser , i'm waiting for customer feedback - thanks for keeping it opened

Nico

Hi Biser,

after discussion with customer the only timing that annoys him is the difference they measure on Delay Time MMC_CLK rise & MMC_DATx transition

Table 7-90 &Figure 7-95 : Delay Time MMC_CLK rise & MMC_DATx transition is specified at Max 14ns @ OPP100 in High speed mode 

Customer is measuring 17.8ns which is higher than specification 

Customer is asking to clarify , eventually measure  & update datasheet if it needs to be .

Thanks

Best Regards

Nicolas

I'm forwarding this to the factory team. They will respond here.

The MMC/SD/SDIO output signals can be driven on either falling edge or rising edge of clock depending on the HSPE bit in the SD_HCTL register.

 

When the HSPE bit is cleared (0), data is driven on the falling edge of clock.

When the HSPE bit is set (1), data is driven on the rising edge of clock.

 

What is the value of HSPE when measuring the delay?

 

Regards,
Paul